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Inspired by the #100daysofrtl challenge and @raulbehl to learn SystemVerilog by coding a module every day and improve my design and verification skills.

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Marcotronics/100daysofRTL

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100daysofRTL

Inspired by the #100daysofrtl challenge and @raulbehl to learn SystemVerilog by coding a module every day and improve my design and verification skills.

Here is the link to @raulbehl profile: Link

Day Module Github Link
1 Day_1_RTL_MUX https://github.com/Marcotronics/100daysofRTL/001_RTL_MUX
2 Day_2_RTL_D_LATCH https://github.com/Marcotronics/100daysofRTL/002_RTL_D_LATCH
3 Day_3_RTL_D_FF https://github.com/Marcotronics/100daysofRTL/003_D_FF
4 Day_4_RTL_8BIT_COUNTER https://github.com/Marcotronics/100daysofRTL/004_RTL_8BIT_COUNTER
5 Day_5_RTL_BINARY2ONEHOT https://github.com/Marcotronics/100daysofRTL/005_RTL_BINARY2ONEHOT
6 Day_6_RTL_BINARY2GRAY https://github.com/Marcotronics/100daysofRTL/006_RTL_BINARY2GRAY
7 Day_7_RTL_ALU https://github.com/Marcotronics/100daysofRTL/007_RTL_ALU
8 Day_8_RTL_SHIFT_REGISTER https://github.com/Marcotronics/100daysofRTL/008_SHIFT_REGISTER
9 Day_9_RTL_LFSR https://github.com/Marcotronics/100daysofRTL/009_RTL_LFSR
10 Day_10_RTL_PISO_SR https://github.com/Marcotronics/100daysofRTL/010_RTL_PISO_SR
11 Day_11_RTL_LOAD_COUNTER https://github.com/Marcotronics/100daysofRTL/011_RTL_LOAD_COUNTER
12 Day_12_JOHNSON_COUNTER https://github.com/Marcotronics/100daysofRTL/012_JOHNSON_COUNTER
13 Day_13_SEQUENCE_DETECTOR https://github.com/Marcotronics/100daysofRTL/013_SEQUENCE_DETECTOR

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Inspired by the #100daysofrtl challenge and @raulbehl to learn SystemVerilog by coding a module every day and improve my design and verification skills.

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