AXI4 and AXI4-Lite interface definitions

Engineering Program on RTL Design for FPGA Accelerator

AMBA bus generator including AXI4, AXI3, AHB, and APB

RISC-V Cores, SoC platforms and SoCs

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieve…

A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence generates addresses and allows the driver to tell the BFM which …

Verilog SDRAM memory controller

An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图像解码器，可以从PNG文件中解码出原始像素。

An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

uvm-1.2 library files from: http:https://www.accellera.org/images/downloads/standards/uvm/uvm-1.2.tar.gz

A roadmap for those who want to build a career as an FPGA / ASIC Engineer

HMC (Hybrid Memory Cube) Controller Verification Graduation project under the supervision of Si-Vision.

A simple synch FIFO designed in Verilog and verified in UVM methodology including scoreboards, coverage collector, also code coverage and functional coverage reports etc.

Verification of ALU using System Verilog, The 1st project for ITI 3 Months Digital Verification Track.

Functional Verification of UART Protocol using UVM methodology. A Serial Inter System Communication Peripheral Protocol.

Implementation and Functional Verification of I2C Master using UVM methodology.

AMBA bus lecture material

System Verilog using Functional Verification

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation

VHDL implementation of RSA encryption/decryption using Montgomery modular multipliers

Verilog Implementation of modular exponentiation using Montgomery multiplication

Drawio => VHDL and Verilog