Cesar Fuguet
cfuguet
Digital hardware designer and processor architect.
Inria, TIMA Laboratory, University Grenoble Alpes Grenoble, France
Davide Schiavone
davideschiavone
PostDoc at EPFL and Director of Eng. in the OpenHW Group. He received his Ph.D. from ETH Zurich.
EPFL, OpenHW Group Geneva
Ray Salemi
raysalemi
I am the author of the UVM Primer and the Aerospace & Defense Solutions Manager at Siemens EDA DVT division.
Siemens EDA Boston, MA
RISC-V Administrative Materials
riscv-admin
The Open-Standard Instruction Set Architecture
Zurich, CH
RISC-V Non-ISA Specifications
riscv-non-isa
The Open-Standard Instruction Set Architecture
Switzerland
Mike Thompson
MikeOpenHWGroup
Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Group.
@openhwgroup Ottawa, Ontario, Canada