projetASN

L’objectif de ce projet est de concevoir un microprocesseur de type RISC 4 bits

Name		Name	Last commit message	Last commit date
Latest commit History 46 Commits
db		db
output_files		output_files
simulation/modelsim		simulation/modelsim
ALU.vhd		ALU.vhd
CPU.bdf		CPU.bdf
CPU.qpf		CPU.qpf
CPU.qsf		CPU.qsf
CPU.qws		CPU.qws
CPU.sdc		CPU.sdc
CPU.vhd		CPU.vhd
CPU.vhd.bak		CPU.vhd.bak
CPU_assignment_defaults.qdf		CPU_assignment_defaults.qdf
CPU_nativelink_simulation.rpt		CPU_nativelink_simulation.rpt
Event_Detect.bsf		Event_Detect.bsf
Event_Detect.vhd		Event_Detect.vhd
Fetch.vhd		Fetch.vhd
README.md		README.md
RISC.pdf		RISC.pdf
Ram.vhd		Ram.vhd
Rom.vhd		Rom.vhd
SEG7_LUT.bsf		SEG7_LUT.bsf
SEG7_LUT.cmp		SEG7_LUT.cmp
SEG7_LUT.vhd		SEG7_LUT.vhd
decoder.vhd		decoder.vhd
dig2dec.bsf		dig2dec.bsf
dig2dec.cmp		dig2dec.cmp
dig2dec.vhd		dig2dec.vhd
ram.bsf		ram.bsf
register_file.vhd		register_file.vhd
rom.bsf		rom.bsf
test_alu.vhd		test_alu.vhd
test_cpu.vhd		test_cpu.vhd
test_decoder.vhd		test_decoder.vhd
test_rf.vhd		test_rf.vhd

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