Welcome to my #100daysofRTL In this repo, I'll be documenting my daily progress as I delve into the world of RTL design.🙌
Becoming a successful RTL designer involves taking systematic steps, and I've outlined a structured approach in my #100daysofRTL journey. Over the course of 100 days, my goal is to create, code, and validate various logic designs using Hardware Description Language (HDL) while employing High-Level Verification (HVL) techniques. With determination and perseverance, I aim to make the most of this journey and emerge as a proficient RTL engineer. Let's keep moving forward and strive for excellence!🤓
- Day 001: 16:1 Mux
- Day 002: BCD to Excess 3
- Day 003: 3-bit subractor
- Day 004: Arithematic Logic Unit
- Day 005: SR Flipflop
- Day 006: D Flipflop
- Day 007: JK Flipflop
- Day 008: T Flipflop
- Day 009: 8-bit Up/Down Counter
- Day 010: Ring Counter
- Day 011: Ripple Carry Adder
- Day 012: Ripple Counter
- 16x1 Multiplexer using structural modeling
- BCD to Excess 3 code converter using 4 to 10 decoders with active high outputs and a minimum no. of gate primitives
- 3-bit subtractor by instantiating the half_sub module
- Arithmetic Logic Unit (ALU) using behavioural modeling and case statements
- SR Flipflop using dataflow modeling
- D Flipflop using dataflow modeling
- JK Flipflop with an asynchronous set and reset at the gate level
- T flipflop using a D flipflop.
- 8-bit Up/Down Counter Module using non-blocking procedural assignment
- 8:1 mux using blocking procedural assignment
- Parameterized Ring Counter module using the non-blocking procedural assignment
- Parameterized ripple carry adder using the generate block assignment
- Ripple counter using user-defined primitives
- Full Adder using user-defined primitives
- Majority Detector using user-defined primitives
I hope you find this repository informative and inspiring. Feel free to follow along with my progress, and don't hesitate to reach out if you have any questions or suggestions. Let's embark on this RTL design journey together!