Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Treat sub and div as induction in simd loop lowering #22268

Merged
merged 1 commit into from
Jun 11, 2017
Merged

Treat sub and div as induction in simd loop lowering #22268

merged 1 commit into from
Jun 11, 2017

Conversation

yuyichao
Copy link
Contributor

@yuyichao yuyichao commented Jun 7, 2017

This makes sure induction like

s -= a[i]

in an at-simd loop can be vectorized without fastmath annotation.

LLVM currently support at least sub in the vectorizer.
I don't see why it can't handle div so let's first make sure we are ready for that.

@nanosoldier runbenchmarks(ALL, vs = ":master")

@yuyichao yuyichao added the compiler:codegen Generation of LLVM IR and native code label Jun 7, 2017
@yuyichao
Copy link
Contributor Author

yuyichao commented Jun 7, 2017

The LLVM issue for not vectorizing induction on fdiv is reported at https://bugs.llvm.org//show_bug.cgi?id=33345 .

@nanosoldier
Copy link
Collaborator

Your benchmark job has completed - possible performance regressions were detected. A full report can be found here. cc @jrevels

@yuyichao
Treat sub and div as induction in simd loop lowering
3f3d8b3 
This makes sure induction like

```julia
s -= a[i]
```

in an at-simd loop can be vectorized without fastmath annotation.

LLVM currently support at least sub in the vectorizer.
I don't see why it can't handle div so let's first make sure we are ready for that.
@yuyichao
Copy link
Contributor Author

@nanosoldier runbenchmarks(ALL, vs = ":master")

@nanosoldier
Copy link
Collaborator

Something went wrong when running your job:

NanosoldierError: failed to run benchmarks against primary commit: failed process: Process(`make -j3`, ProcessExited(2)) [2]

Logs and partial data can be found here
cc @jrevels

@yuyichao
Copy link
Contributor Author

llvm-config error on nanosoldier?

@yuyichao yuyichao merged commit 4285a10 into master Jun 11, 2017
@yuyichao yuyichao deleted the yyc/codegen/simd-sub branch June 11, 2017 13:43
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
compiler:codegen Generation of LLVM IR and native code
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@yuyichao @nanosoldier