Implementation of RISCV32I Single Cycle Architecture consisting of six base instructions (R, I, B, S, J, U).

TCL Workshop: From Introduction to Advanced Scripting Techniques in Design and Synthesis

communication and bus protocol

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

VSD Research Program

Solve one design problem each day for a month

Modular hardware build system

Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology

Repository for VSD-IAT Workshop: Physical Verification using SKY130

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSI…

Physical Verification using skywater 130nm

OpenROAD's unified application implementing an RTL-to-GDS Flow

[HISTORICAL] RISC-V ISA Extensions and Standard Hash Functions (contributions in 2020)

A list of resources related to the open-source FPGA projects

😎 A curated list of awesome GitHub Profile which updates in real time

100 Days of RTL

Neural Networks: Zero to Hero

This script generates and analyzes prefix tree adders.

challenges-SoumitroV created by GitHub Classroom

challenges-Jayanth-sharma created by GitHub Classroom

Verilog RTL Design

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.