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Grande-Risco-5 Public
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
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riscv-learn Public
Forked from riscv/learnTracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
1 UpdatedNov 6, 2024 -
riscv-openocd Public
Forked from riscv-collab/riscv-openocdFork of OpenOCD that has RISC-V support
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yosys Public
Forked from YosysHQ/yosysYosys Open SYnthesis Suite
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Baby-Risco-5 Public
Multi-cycle RISC-V processor with RV32E implementation
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Risco-5 Public
Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.
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Risco-5S Public
RISC-V Simulator with RV32IM implementation, built during a few days off.
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AUK-V-Aethia Public
Forked from veeYceeY/AUK-V-AethiaAUK-V RV32I CPU
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Este projeto tem como objetivo principal o desenvolvimento de um Music Player utilizando FPGA (Field-Programmable Gate Array) e PWM (Pulse Width Modulation).
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openFPGALoader Public
Forked from trabucayre/openFPGALoaderUniversal utility for programming FPGA
C++ Apache License 2.0 UpdatedJul 13, 2024 -
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riscv-steel Public
Forked from riscv-steel/riscv-steelFree collection of RISC-V IP cores.
Verilog MIT License UpdatedJun 15, 2024 -
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darkriscv Public
Forked from darklife/darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Verilog BSD 3-Clause "New" or "Revised" License UpdatedApr 3, 2024 -
estudos_verilog Public
Exemplos feito em verilog para estudos
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Pequeno-Risco-5 Public
Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.
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nes_colorlight Public
Forked from nand2mario/nestangNESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
Verilog GNU General Public License v3.0 UpdatedMar 13, 2024 -
explore Public
Forked from github/exploreCommunity-curated topic and collection pages on GitHub
Ruby Creative Commons Attribution 4.0 International UpdatedFeb 24, 2024 -
nerv Public
Forked from YosysHQ/nervNaive Educational RISC V processor
SystemVerilog Other UpdatedFeb 16, 2024 -
serv Public
Forked from olofk/servSERV - The SErial RISC-V CPU
Verilog ISC License UpdatedJan 22, 2024 -
riscv-isa-ci Public archive
CI/CD for RISC-V Cores
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picorv32 Public
Forked from YosysHQ/picorv32PicoRV32 - A Size-Optimized RISC-V CPU
Verilog ISC License UpdatedNov 17, 2023 -
tinyriscv Public
Forked from liangkangnan/tinyriscvA very simple and easy to understand RISC-V core.
C Apache License 2.0 UpdatedNov 7, 2023 -
biriscv Public
Forked from ultraembedded/biriscv32-bit Superscalar RISC-V CPU
Verilog Apache License 2.0 UpdatedNov 7, 2023
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