RISC-V implementation of a vector accelerator that will eventually be used to accelerate Machine Learning algorithms. We are compliant with latest version of the RISC-V Vector ISA (currently v1.0). We plan on supporting special types such as bfloat16 and posits to accelerate these workloads.

More details can be found in our report and paper.

For any clarification, do not hesitate to contact Imad Al Assir or Mohammad El Iskandarani