Merge pull request #387 from HyperDbg/hwdbg-script

Hwdbg script

hwdbg/sim/hwdbg/DebuggerModuleTestingBRAM/Makefile

@@ -9,9 +9,10 @@ VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketReceiver.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketSender.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/DebuggerPacketInterpreter.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterInstanceInfo.sv
-VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterSendError.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterSendSuccessOrError.sv
 VERILOG_SOURCES += $(shell pwd)/../../../generated/ScriptExecutionEngine.sv
-VERILOG_SOURCES += $(shell pwd)/../../../generated/ScriptEngineEval.sv
+VERILOG_SOURCES += $(shell pwd)/../../../generated/InterpreterScriptBufferHandler.sv
+#VERILOG_SOURCES += $(shell pwd)/../../../generated/ScriptEngineEval.sv
 TOPLEVEL = DebuggerModuleTestingBRAM
 MODULE = test_DebuggerModuleTestingBRAM
 

hwdbg/sim/hwdbg/DebuggerModuleTestingBRAM/bram_instance_info.txt

@@ -1,18 +1,18 @@
 Content of BRAM after emulation:
 
 PS to PL area:
-mem_0: 0000005a | Checksum
+mem_0: 000000d3 | Checksum
 mem_1: 00000000 | Checksum
 mem_2: 52444247 | Indicator
 mem_3: 48595045 | Indicator
 mem_4: 00000004 | TypeOfThePacket
-mem_5: 00000001 | RequestedActionOfThePacket
-mem_6: 00000000 | Start of Optional Data
-mem_7: 00000000
-mem_8: 00000000
-mem_9: 00000000
-mem_10: 00000000
-mem_11: 00000000
+mem_5: 00000002 | RequestedActionOfThePacket
+mem_6: 55021005 | Start of Optional Data
+mem_7: 00060003
+mem_8: 0c021605
+mem_9: 1d050006
+mem_10: 00038502
+mem_11: 0c021505
 mem_12: 00000000
 mem_13: 00000000
 mem_14: 00000000
@@ -133,24 +133,24 @@ mem_127: 00000000
 PL to PS area:
 mem_128: 00000000 | Checksum
 mem_129: 00000000 | Checksum
-mem_130: 52444247 | Indicator
-mem_131: 48595045 | Indicator
-mem_132: 00000005 | TypeOfThePacket
-mem_133: 00000002 | RequestedActionOfThePacket
-mem_134: 00000100 | Start of Optional Data
-mem_135: 0000000a
-mem_136: 00000008
-mem_137: 00000002
-mem_138: 00000001
-mem_139: 00000400
+mem_130: 00000000 | Indicator
+mem_131: 00000000 | Indicator
+mem_132: 00000000 | TypeOfThePacket
+mem_133: 00000000 | RequestedActionOfThePacket
+mem_134: 00000000 | Start of Optional Data
+mem_135: 00000000
+mem_136: 00000000
+mem_137: 00000000
+mem_138: 00000000
+mem_139: 00000000
 mem_140: 00000000
-mem_141: 00000200
-mem_142: 00000020
-mem_143: 00000002
-mem_144: 003fffdf
+mem_141: 00000000
+mem_142: 00000000
+mem_143: 00000000
+mem_144: 00000000
 mem_145: 00000000
-mem_146: 0000000c
-mem_147: 00000014
+mem_146: 00000000
+mem_147: 00000000
 mem_148: 00000000
 mem_149: 00000000
 mem_150: 00000000

hwdbg/src/main/scala/hwdbg/communication/interpreter.scala

@@ -21,6 +21,7 @@ import circt.stage.ChiselStage
 
 import hwdbg.configs._
 import hwdbg.types._
+import hwdbg.script._
 
 object DebuggerPacketInterpreterEnums {
  object State extends ChiselEnum {
@@ -72,6 +73,12 @@ class DebuggerPacketInterpreter(
  val requestedActionOfThePacketOutput = Output(UInt(new DebuggerRemotePacket().RequestedActionOfThePacket.getWidth.W)) // the requested action
  val sendingData = Output(UInt(bramDataWidth.W)) // data to be sent to the debugger
 
+ //
+ // Script stage configuration signals
+ //
+ val moveToNextStage = Output(Bool()) // whether configuration finished configuring the current stage or not?
+ val configureStage = Output(Bool()) // whether the configuration of stage should start or not?
+ val targetOperator = Output(new HwdbgShortSymbol(instanceInfo.scriptVariableLength)) // Current operator to be configured
  })
 
  //
@@ -82,7 +89,7 @@ class DebuggerPacketInterpreter(
  //
  // Last error register
  //
- val lastError = RegInit(0.U(bramDataWidth.W))
+ val lastSuccesOrErrorMessage = RegInit(0.U(bramDataWidth.W))
 
  //
  // Output pins
@@ -97,6 +104,13 @@ class DebuggerPacketInterpreter(
 
  val regRequestedActionOfThePacketOutput = RegInit(0.U(new DebuggerRemotePacket().RequestedActionOfThePacket.getWidth.W))
 
+ val moveToNextStage = WireInit(false.B)
+ val configureStage = WireInit(false.B)
+ val initialSymbol = Wire(new HwdbgShortSymbol(instanceInfo.scriptVariableLength))
+ initialSymbol.Type := 0.U
+ initialSymbol.Value := 0.U
+ val targetOperator = WireInit(initialSymbol)
+
  //
  // Apply the chip enable signal
  //
@@ -153,16 +167,62 @@ class DebuggerPacketInterpreter(
  //
  // *** Configure the internal buffer with script ***
  //
+ val (
+ readNextData,
+ finishedConfiguration,
+ moduleConfigureStage,
+ moduleMoveToNextStage,
+ moduleTargetOperator
+ ) =
+ InterpreterScriptBufferHandler(
+ debug,
+ instanceInfo,
+ bramDataWidth
+ )(
+ io.en,
+ io.dataValidInput,
+ io.receivingData
+ )
 
  //
- // Set the response packet type
+ // Connect the script stage configuration signals
  //
- regRequestedActionOfThePacketOutput := HwdbgResponseEnums.hwdbgResponseScriptBufferConfigurationResult.id.U
+ configureStage := moduleConfigureStage
+ moveToNextStage := moduleMoveToNextStage
+ targetOperator := moduleTargetOperator
 
- //
- // This action needs a response
- //
- state := sSendResponse
+ when (finishedConfiguration === true.B) {
+
+ //
+ // *** Script stage buffer configuration finished! ***
+ //
+
+ //
+ // Set the response packet type
+ //
+ regRequestedActionOfThePacketOutput := HwdbgResponseEnums.hwdbgResponseSuccessOrErrorMessage.id.U
+
+ //
+ // Set the success message 
+ //
+ lastSuccesOrErrorMessage := HwdbgSuccessOrErrorEnums.hwdbgOperationWasSuccessful.id.U
+
+ //
+ // This action needs a response
+ //
+ state := sSendResponse
+
+ }.otherwise {
+
+ //
+ // *** Script stage buffer configuration NOT finished, read the buffer ***
+ //
+
+ //
+ // Stay at the same state
+ //
+ state := sNewActionReceived
+ }
 
  }.otherwise {
 
@@ -173,12 +233,12 @@ class DebuggerPacketInterpreter(
  //
  // Set the response packet type
  //
- regRequestedActionOfThePacketOutput := HwdbgResponseEnums.hwdbgResponseInvalidPacketOrError.id.U
+ regRequestedActionOfThePacketOutput := HwdbgResponseEnums.hwdbgResponseSuccessOrErrorMessage.id.U
 
  //
  // Set the latest error
  //
- lastError := HwdbgErrorEnums.hwdbgErrorInvalidPacket.id.U
+ lastSuccesOrErrorMessage := HwdbgSuccessOrErrorEnums.hwdbgErrorInvalidPacket.id.U
 
  //
  // This action needs a response
@@ -252,22 +312,10 @@ class DebuggerPacketInterpreter(
  state := sDone
  }
 
- }.elsewhen(regRequestedActionOfThePacketOutput === HwdbgResponseEnums.hwdbgResponseScriptBufferConfigurationResult.id.U) {
-
- //
- // *** Send result of applying script ***
- //
+ }.elsewhen(regRequestedActionOfThePacketOutput === HwdbgResponseEnums.hwdbgResponseSuccessOrErrorMessage.id.U) {
 
  //
- // TODO: To be implemented
- //
- state := sDone
-
- }.otherwise {
-
- //
- // *** Invalid (packet) response ***
- // This will happen in case of 'HwdbgResponseEnums.hwdbgResponseInvalidPacketOrError'
+ // *** Send result of applying command (and errors) ***
  //
 
  //
@@ -278,12 +326,12 @@ class DebuggerPacketInterpreter(
  dataValidOutputModule,
  sendingDataModule
  ) =
- InterpreterSendError(
+ InterpreterSendSuccessOrError(
  debug,
  bramDataWidth
  )(
  io.sendWaitForBuffer, // send waiting for buffer as an activation signal to the module
- lastError
+ lastSuccesOrErrorMessage
  )
 
  //
@@ -352,6 +400,9 @@ class DebuggerPacketInterpreter(
  io.requestedActionOfThePacketOutput := regRequestedActionOfThePacketOutput
  io.sendingData := sendingData
 
+ io.configureStage := configureStage
+ io.moveToNextStage := moveToNextStage
+ io.targetOperator := targetOperator
 }
 
 object DebuggerPacketInterpreter {
@@ -368,7 +419,7 @@ object DebuggerPacketInterpreter {
  dataValidInput: Bool,
  receivingData: UInt,
  sendWaitForBuffer: Bool
- ): (Bool, Bool, Bool, Bool, Bool, UInt, UInt) = {
+ ): (Bool, Bool, Bool, Bool, Bool, UInt, UInt, Bool, Bool, HwdbgShortSymbol) = {
 
  val debuggerPacketInterpreter = Module(
  new DebuggerPacketInterpreter(
@@ -389,6 +440,10 @@ object DebuggerPacketInterpreter {
  val requestedActionOfThePacketOutput = Wire(UInt(new DebuggerRemotePacket().RequestedActionOfThePacket.getWidth.W))
  val sendingData = Wire(UInt(bramDataWidth.W))
 
+ val moveToNextStage = Wire(Bool())
+ val configureStage = Wire(Bool())
+ val targetOperator = Wire(new HwdbgShortSymbol(instanceInfo.scriptVariableLength))
+
  //
  // Configure the input signals
  //
@@ -426,6 +481,13 @@ object DebuggerPacketInterpreter {
  requestedActionOfThePacketOutput := debuggerPacketInterpreter.io.requestedActionOfThePacketOutput
  sendingData := debuggerPacketInterpreter.io.sendingData
 
+ //
+ // Configure the output signals related to stage configuration
+ //
+ moveToNextStage := debuggerPacketInterpreter.io.moveToNextStage
+ configureStage := debuggerPacketInterpreter.io.configureStage
+ targetOperator := debuggerPacketInterpreter.io.targetOperator
+
  //
  // Return the output result
  //
@@ -436,7 +498,10 @@ object DebuggerPacketInterpreter {
  noNewDataSender,
  dataValidOutput,
  requestedActionOfThePacketOutput,
- sendingData
+ sendingData,
+ moveToNextStage,
+ configureStage,
+ targetOperator
  )
  }
 }