v0.9

HyperDbg · Jun 9, 2024 · 5897065 · 5897065
2 parents 3890408 + 820d9ce
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -4,11 +4,20 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## [0.8.5.0] - 2024-05-XX
+## [0.9.0.0] - 2024-06-09
 New release of the HyperDbg Debugger.
 
+### Added
+- The **!monitor** command now physical address hooking ([link](https://docs.hyperdbg.org/commands/extension-commands/monitor))
+- **hwdbg** is merged to HyperDbg codebase ([link](https://hwdbg.hyperdbg.org))
+- **strncmp(Str1, Str2, Num)**, and **wcsncmp(WStr1, WStr2, Num)** functions in script engine ([link](https://docs.hyperdbg.org/commands/scripting-language/functions/strings/strncmp))([link](https://docs.hyperdbg.org/commands/scripting-language/functions/strings/wcsncmp))
+
 ### Changed
+- Using a separate HOST IDT in VMCS (not OS IDT) (fix to this [VM escape](https://www.unknowncheats.me/forum/c-and-c-/390593-vm-escape-via-nmi.html) issues)
+- Using a dedicated HOST GDT and TSS Stack
+- Checking for race-condition of not locked cores before applying instant-events and switching cores
 - The error message for invalid address is changed ([more information](https://docs.hyperdbg.org/tips-and-tricks/considerations/accessing-invalid-address))
+- Fix the problem of not locking all cores after running the '.pagein' command
 
 ## [0.8.4.0] - 2024-05-10
 New release of the HyperDbg Debugger.

diff --git a/README.md b/README.md
@@ -125,6 +125,9 @@ You can also read [this article](https://research.hyperdbg.org/debugger/kernel-d
 ### Eighth Release (v0.8.0.0)
 * Detect kernel-to-user and user-to-kernel transitions [<a href="https://docs.hyperdbg.org/commands/extension-commands/mode" target="_blank">link</a>]
 
+### Ninth Release (v0.9.0.0)
+* Physical memory monitoring hooks [<a href="https://docs.hyperdbg.org/commands/extension-commands/monitor" target="_blank">link</a>]
+
 ## How does it work?
 
 You can read about the internal design of HyperDbg and its features in the [documentation](https://docs.hyperdbg.org/design). Here's a top-level diagram that shows how HyperDbg works:

diff --git a/hwdbg/src/main/scala/hwdbg/communication/interpreter.scala b/hwdbg/src/main/scala/hwdbg/communication/interpreter.scala
@@ -30,8 +30,9 @@ object DebuggerPacketInterpreterEnums {
 
 class DebuggerPacketInterpreter(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ instanceInfo: HwdbgInstanceInformation,
+ bramAddrWidth: Int,
+ bramDataWidth: Int
 ) extends Module {
 
  //
@@ -243,6 +244,7 @@ class DebuggerPacketInterpreter(
  ) =
  InterpreterSendVersion(
  debug,
+ instanceInfo,
  bramDataWidth
  )(
  io.sendWaitForBuffer // send waiting for buffer as an activation signal to the module
@@ -282,6 +284,7 @@ class DebuggerPacketInterpreter(
  ) =
  InterpreterPortInformation(
  debug,
+ instanceInfo,
  bramDataWidth
  )(
  io.sendWaitForBuffer // send waiting for buffer as an activation signal to the module
@@ -410,8 +413,9 @@ object DebuggerPacketInterpreter {
 
  def apply(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ instanceInfo: HwdbgInstanceInformation,
+ bramAddrWidth: Int,
+ bramDataWidth: Int
  )(
  en: Bool,
  requestedActionOfThePacketInput: UInt,
@@ -424,6 +428,7 @@ object DebuggerPacketInterpreter {
  val debuggerPacketInterpreter = Module(
  new DebuggerPacketInterpreter(
  debug,
+ instanceInfo,
  bramAddrWidth,
  bramDataWidth
  )

diff --git a/hwdbg/src/main/scala/hwdbg/communication/interpreter/port_information.scala b/hwdbg/src/main/scala/hwdbg/communication/interpreter/port_information.scala
@@ -19,7 +19,6 @@ import chisel3._
 import chisel3.util.{switch, is, log2Ceil}
 import circt.stage.ChiselStage
 
-import hwdbg.version._
 import hwdbg.configs._
 import hwdbg.utils._
 
@@ -31,8 +30,8 @@ object InterpreterPortInformationEnums {
 
 class InterpreterPortInformation(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
- portsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP
+ instanceInfo: HwdbgInstanceInformation,
+ bramDataWidth: Int
 ) extends Module {
 
  //
@@ -65,12 +64,12 @@ class InterpreterPortInformation(
  //
  // Get number of input/output ports
  //
- val numberOfPorts = portsConfiguration.size
+ val numberOfPorts = instanceInfo.portsConfiguration.size
 
  //
  // Convert input port pins into vector
  //
- // val pinsVec = VecInit(portsConfiguration.values.toSeq.map(_.U))
+ // val pinsVec = VecInit(instanceInfo.portsConfiguration.values.toSeq.map(_.U))
  val pinsVec = RegInit(VecInit(Seq.fill(numberOfPorts)(0.U(bramDataWidth.W))))
 
  //
@@ -123,9 +122,11 @@ class InterpreterPortInformation(
  //
  LogInfo(debug)("Iterating over input pins:")
 
- portsConfiguration.foreach { case (port, pins) =>
- LogInfo(debug)(s"Port $port has $pins pins")
- pinsVec(port) := pins.U
+ var portNum: Int = 0
+ for (pin <- instanceInfo.portsConfiguration) {
+ LogInfo(debug)(s"Port $portNum has $pin pins")
+ pinsVec(portNum) := pin.U
+ portNum = portNum + 1
  }
 
  //
@@ -204,17 +205,17 @@ object InterpreterPortInformation {
 
  def apply(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
- portsConfiguration: Map[Int, Int] = DebuggerPorts.PORT_PINS_MAP
+ instanceInfo: HwdbgInstanceInformation,
+ bramDataWidth: Int,
  )(
  en: Bool
  ): (Bool, Bool, UInt) = {
 
  val interpreterPortInformation = Module(
  new InterpreterPortInformation(
  debug,
- bramDataWidth,
- portsConfiguration
+ instanceInfo,
+ bramDataWidth
  )
  )
 

diff --git a/hwdbg/src/main/scala/hwdbg/communication/interpreter/send_error.scala b/hwdbg/src/main/scala/hwdbg/communication/interpreter/send_error.scala
@@ -19,12 +19,11 @@ import chisel3._
 import chisel3.util.{switch, is}
 import circt.stage.ChiselStage
 
-import hwdbg.version._
 import hwdbg.configs._
 
 class InterpreterSendError(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ bramDataWidth: Int
 ) extends Module {
 
  val io = IO(new Bundle {
@@ -84,7 +83,7 @@ object InterpreterSendError {
 
  def apply(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ bramDataWidth: Int
  )(
  en: Bool,
  lastError: UInt

diff --git a/hwdbg/src/main/scala/hwdbg/communication/interpreter/send_version.scala b/hwdbg/src/main/scala/hwdbg/communication/interpreter/send_version.scala
@@ -19,12 +19,12 @@ import chisel3._
 import chisel3.util.{switch, is}
 import circt.stage.ChiselStage
 
-import hwdbg.version._
 import hwdbg.configs._
 
 class InterpreterSendVersion(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ instanceInfo: HwdbgInstanceInformation,
+ bramDataWidth: Int
 ) extends Module {
 
  val io = IO(new Bundle {
@@ -83,14 +83,16 @@ object InterpreterSendVersion {
 
  def apply(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ instanceInfo: HwdbgInstanceInformation,
+ bramDataWidth: Int
  )(
  en: Bool
  ): (Bool, Bool, UInt) = {
 
  val interpreterSendVersion = Module(
  new InterpreterSendVersion(
  debug,
+ instanceInfo,
  bramDataWidth
  )
  )

diff --git a/hwdbg/src/main/scala/hwdbg/communication/receiver.scala b/hwdbg/src/main/scala/hwdbg/communication/receiver.scala
@@ -33,8 +33,8 @@ object DebuggerPacketReceiverEnums {
 
 class DebuggerPacketReceiver(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ bramAddrWidth: Int,
+ bramDataWidth: Int
 ) extends Module {
 
  //
@@ -379,8 +379,8 @@ object DebuggerPacketReceiver {
 
  def apply(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ bramAddrWidth: Int,
+ bramDataWidth: Int
  )(
  en: Bool,
  plInSignal: Bool,

diff --git a/hwdbg/src/main/scala/hwdbg/communication/send_receive_synchronizer.scala b/hwdbg/src/main/scala/hwdbg/communication/send_receive_synchronizer.scala
@@ -30,8 +30,8 @@ object SendReceiveSynchronizerEnums {
 
 class SendReceiveSynchronizer(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ bramAddrWidth: Int,
+ bramDataWidth: Int
 ) extends Module {
 
  //
@@ -305,8 +305,8 @@ object SendReceiveSynchronizer {
 
  def apply(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ bramAddrWidth: Int,
+ bramDataWidth: Int
  )(
  en: Bool,
  plInSignal: Bool,

diff --git a/hwdbg/src/main/scala/hwdbg/communication/sender.scala b/hwdbg/src/main/scala/hwdbg/communication/sender.scala
@@ -31,8 +31,8 @@ object DebuggerPacketSenderEnums {
 
 class DebuggerPacketSender(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ bramAddrWidth: Int,
+ bramDataWidth: Int
 ) extends Module {
 
  //
@@ -439,8 +439,8 @@ object DebuggerPacketSender {
 
  def apply(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
- bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+ bramAddrWidth: Int,
+ bramDataWidth: Int
  )(
  en: Bool,
  beginSendingBuffer: Bool,