Merge pull request #394 from HyperDbg/hwdbg-script

Hwdbg script

hwdbg/sim/hwdbg/DebuggerModuleTestingBRAM/bram_instance_info.txt

@@ -139,20 +139,20 @@ mem_132: 00000005 | TypeOfThePacket
 mem_133: 00000002 | RequestedActionOfThePacket
 mem_134: 00000100 | Start of Optional Data
 mem_135: 00000020
-mem_136: 00000020
+mem_136: 00000008
 mem_137: 00000002
 mem_138: 00000001
 mem_139: 00000400
 mem_140: 00000000
 mem_141: 00000200
 mem_142: 00000020
 mem_143: 00000002
-mem_144: 003fffdf
+mem_144: 000ffff7
 mem_145: 00000000
-mem_146: 0000000c
-mem_147: 00000014
-mem_148: 00000000
-mem_149: 00000000
+mem_146: 0000000d
+mem_147: 00000020
+mem_148: 0000000c
+mem_149: 00000014
 mem_150: 00000000
 mem_151: 00000000
 mem_152: 00000000

hwdbg/sim/hwdbg/DebuggerModuleTestingBRAM/script_buffer_response.txt

@@ -1,13 +1,13 @@
 Content of BRAM after emulation:
 
 PS to PL area:
-mem_0: 000000de | Checksum
+mem_0: 000000e2 | Checksum
 mem_1: 00000000 | Checksum
 mem_2: 52444247 | Indicator
 mem_3: 48595045 | Indicator
 mem_4: 00000004 | TypeOfThePacket
 mem_5: 00000002 | RequestedActionOfThePacket
-mem_6: 0000000b | Start of Optional Data
+mem_6: 0000000f | Start of Optional Data
 mem_7: 00000005
 mem_8: 00000010
 mem_9: 00000002
@@ -22,20 +22,20 @@ mem_17: 00000002
 mem_18: 0000000c
 mem_19: 00000006
 mem_20: 00000000
-mem_21: 00000005
-mem_22: 0000001d
-mem_23: 00000002
-mem_24: 00000085
-mem_25: 00000003
-mem_26: 00000000
-mem_27: 00000005
-mem_28: 00000015
-mem_29: 00000002
-mem_30: 0000000c
-mem_31: 00000000
-mem_32: 00000000
-mem_33: 00000000
-mem_34: 00000000
+mem_21: 00000000
+mem_22: 00000000
+mem_23: 00000005
+mem_24: 0000001d
+mem_25: 00000002
+mem_26: 00000085
+mem_27: 00000000
+mem_28: 00000000
+mem_29: 00000003
+mem_30: 00000000
+mem_31: 00000005
+mem_32: 00000015
+mem_33: 00000002
+mem_34: 0000000c
 mem_35: 00000000
 mem_36: 00000000
 mem_37: 00000000

hwdbg/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py

@@ -133,6 +133,7 @@ def print_bram_content(dut):
  sorted_list = sorted(mem_items, key=extract_number)
 
  with open("script_buffer_response.txt", "w") as file:
+ # with open("bram_instance_info.txt", "w") as file:
  file.write("Content of BRAM after emulation:\n")
  print("Content of BRAM after emulation:")
 
@@ -224,6 +225,31 @@ def print_bram_content(dut):
 
  print("\n===================================================================\n")
 
+
+#
+# Define a function to extract content of symbol
+#
+def get_symbol_type_and_value(dut, value, type):
+ element_value = getattr(dut.debuggerMainModule.outputPin_scriptExecutionEngineModule, value)
+ element_type = getattr(dut.debuggerMainModule.outputPin_scriptExecutionEngineModule, type)
+
+ hex_string_value = ""
+ hex_string_type = ""
+ try:
+ int_content_value = int(str(element_value.value), 2)
+ int_content_type = int(str(element_type.value), 2)
+
+ hex_string_value = f'{int_content_value:x}'
+ hex_string_type = f'{int_content_type:x}'
+ except:
+ hex_string_value = str(element_value.value)
+ hex_string_type = str(element_type.value)
+
+ final_string_value = f'{value}: 0x{hex_string_value}' + " (bin: " + str(element_value.value) + ")"
+ final_string_type = f'{type} : 0x{hex_string_type}' + " (bin: " + str(element_type.value) + ")"
+
+ return final_string_value, final_string_type
+
 #
 # Define a function to extract content of stages
 #
@@ -258,48 +284,56 @@ def extract_stage_details(dut):
 
  for index, element in enumerate(sorted_values):
 
- element_values = getattr(dut.debuggerMainModule.outputPin_scriptExecutionEngineModule, sorted_values[index])
- element_types = getattr(dut.debuggerMainModule.outputPin_scriptExecutionEngineModule, sorted_types[index])
+ final_string_type, final_string_value = get_symbol_type_and_value(dut, sorted_values[index], sorted_types[index])
 
  #
- # Print the target register in binary format
+ # Print the value and type
  #
- # print(str(element))
+ print(final_string_type)
+ print(final_string_value)
+
+ print("\n")
 
  #
- # Convert binary to int
+ # Check stage enable bit
  #
- hex_string_value = ""
- hex_string_type = ""
  try:
- int_content_value = ""
- int_content_type = ""
-
- int_content_value = int(str(element_values.value), 2)
- int_content_type = int(str(element_types.value), 2)
-
- #
- # Convert integer to hexadecimal string with at least 8 characters
- #
- hex_string_value = f'{int_content_value:08x}'
- hex_string_type = f'{int_content_type:08x}'
+ stage_enabled = "stageRegs_" + str(index) + "_stageEnable"
+ is_stage_enabled = getattr(dut.debuggerMainModule.outputPin_scriptExecutionEngineModule, stage_enabled)
+ print("\t Stage enabled bit: " + str(is_stage_enabled))
+ except:
+ print("\t Stage enabled bit: (unavailable)")
 
+ try:
+ final_string_type, final_string_value = get_symbol_type_and_value(dut, "stageRegs_" + str(index) + "_getOperatorSymbol_0_Value", "stageRegs_" + str(index) + "_getOperatorSymbol_0_Type")
+
+ print("\t Get (0) | " + final_string_type)
+ print("\t Get (0) | " + final_string_value)
  except:
- hex_string_value = str(element_values.value)
- hex_string_type = str(element_types.value)
+ print("\t stage at:" + str(index) + " does not contain a Get (0) buffer")
 
- final_string_value = sorted_values[index] + ": " + hex_string_value
- final_string_type = sorted_types[index] + " : " + hex_string_type
+ print("\n")
+
+ try:
+ final_string_type, final_string_value = get_symbol_type_and_value(dut, "stageRegs_" + str(index) + "_getOperatorSymbol_1_Value", "stageRegs_" + str(index) + "_getOperatorSymbol_1_Type")
+
+ print("\t Get (1) | " + final_string_type)
+ print("\t Get (1) | " + final_string_value)
+ except:
+ print("\t stage at:" + str(index) + " does not contain a Get (1) buffer")
 
- #
- # Print the value and type
- #
- print(final_string_type)
- print(final_string_value)
  print("\n")
-
 
+ try:
+ final_string_type, final_string_value = get_symbol_type_and_value(dut, "stageRegs_" + str(index) + "_setOperatorSymbol_0_Value", "stageRegs_" + str(index) + "_setOperatorSymbol_0_Type")
+
+ print("\t Set (0) | " + final_string_type)
+ print("\t Set (0) | " + final_string_value)
+ except:
+ print("\t stage at:" + str(index) + " does not contain a Set (0) buffer")
 
+ print("\n\n")
+
 @cocotb.test()
 async def DebuggerModuleTestingBRAM_test(dut):
  """Test hwdbg module (with pre-defined BRAM)"""

hwdbg/src/main/scala/hwdbg/communication/interpreter.scala

@@ -31,9 +31,7 @@ object DebuggerPacketInterpreterEnums {
 
 class DebuggerPacketInterpreter(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- instanceInfo: HwdbgInstanceInformation,
- bramAddrWidth: Int,
- bramDataWidth: Int
+ instanceInfo: HwdbgInstanceInformation
 ) extends Module {
 
  //
@@ -59,7 +57,7 @@ class DebuggerPacketInterpreter(
  val readNextData = Output(Bool()) // whether the next data should be read or not?
 
  val dataValidInput = Input(Bool()) // whether data on the receiving data line is valid or not?
- val receivingData = Input(UInt(bramDataWidth.W)) // data to be received in interpreter
+ val receivingData = Input(UInt(instanceInfo.bramDataWidth.W)) // data to be received in interpreter
 
  //
  // Sending singals
@@ -71,7 +69,7 @@ class DebuggerPacketInterpreter(
  val sendWaitForBuffer = Input(Bool()) // should the interpreter send next buffer or not?
 
  val requestedActionOfThePacketOutput = Output(UInt(new DebuggerRemotePacket().RequestedActionOfThePacket.getWidth.W)) // the requested action
- val sendingData = Output(UInt(bramDataWidth.W)) // data to be sent to the debugger
+ val sendingData = Output(UInt(instanceInfo.bramDataWidth.W)) // data to be sent to the debugger
 
  //
  // Script stage configuration signals
@@ -89,7 +87,7 @@ class DebuggerPacketInterpreter(
  //
  // Last error register
  //
- val lastSuccesOrErrorMessage = RegInit(0.U(bramDataWidth.W))
+ val lastSuccesOrErrorMessage = RegInit(0.U(instanceInfo.bramDataWidth.W))
 
  //
  // Last error register
@@ -105,7 +103,7 @@ class DebuggerPacketInterpreter(
  val regBeginSendingBuffer = RegInit(false.B)
  val noNewDataSender = WireInit(false.B)
  val dataValidOutput = WireInit(false.B)
- val sendingData = WireInit(0.U(bramDataWidth.W))
+ val sendingData = WireInit(0.U(instanceInfo.bramDataWidth.W))
 
  val regRequestedActionOfThePacketOutput = RegInit(0.U(new DebuggerRemotePacket().RequestedActionOfThePacket.getWidth.W))
 
@@ -186,8 +184,7 @@ class DebuggerPacketInterpreter(
  ) =
  InterpreterScriptBufferHandler(
  debug,
- instanceInfo,
- bramDataWidth
+ instanceInfo
  )(
  enablePinOfScriptBufferHandler,
  io.dataValidInput,
@@ -306,8 +303,7 @@ class DebuggerPacketInterpreter(
  ) =
  InterpreterInstanceInfo(
  debug,
- instanceInfo,
- bramDataWidth
+ instanceInfo
  )(
  io.sendWaitForBuffer // send waiting for buffer as an activation signal to the module
  )
@@ -345,7 +341,7 @@ class DebuggerPacketInterpreter(
  ) =
  InterpreterSendSuccessOrError(
  debug,
- bramDataWidth
+ instanceInfo
  )(
  io.sendWaitForBuffer, // send waiting for buffer as an activation signal to the module
  lastSuccesOrErrorMessage
@@ -426,9 +422,7 @@ object DebuggerPacketInterpreter {
 
  def apply(
  debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
- instanceInfo: HwdbgInstanceInformation,
- bramAddrWidth: Int,
- bramDataWidth: Int
+ instanceInfo: HwdbgInstanceInformation
  )(
  en: Bool,
  requestedActionOfThePacketInput: UInt,
@@ -441,9 +435,7 @@ object DebuggerPacketInterpreter {
  val debuggerPacketInterpreter = Module(
  new DebuggerPacketInterpreter(
  debug,
- instanceInfo,
- bramAddrWidth,
- bramDataWidth
+ instanceInfo
  )
  )
 
@@ -455,7 +447,7 @@ object DebuggerPacketInterpreter {
  val dataValidOutput = Wire(Bool())
 
  val requestedActionOfThePacketOutput = Wire(UInt(new DebuggerRemotePacket().RequestedActionOfThePacket.getWidth.W))
- val sendingData = Wire(UInt(bramDataWidth.W))
+ val sendingData = Wire(UInt(instanceInfo.bramDataWidth.W))
 
  val finishedScriptConfiguration = Wire(Bool())
  val configureStage = Wire(Bool())