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1. cv32e41s cv32e41s Public

   Forked from openhwgroup/cv32e40s

   4 stage, in-order, secure RISC-V core based on the CV32E40S

   SystemVerilog 3

2. bourbon-ristretto-32-riscv bourbon-ristretto-32-riscv Public

   A 32-bit RISC-V core built just for fun and learning purposes

   SystemVerilog

3. JNES-a-Java-NES-Emulator JNES-a-Java-NES-Emulator Public

   A Java NES emulator developed during Mc.S. in collaboration with Francesco Vitale and Daniele Ottaviano

   Java

4. SHA256-Accelerator SHA256-Accelerator Public

   This is an implementation of the SHA256 hash function as a custom device in FPGA. The device is AXI compliant both in FULL and LIGHT version of the protocol. (This is a university project coded in …

   VHDL

5. Simple-Pipelined-Processor Simple-Pipelined-Processor Public

   VHDL

6. cv32e41s_SoC_env cv32e41s_SoC_env Public

   A simulation platform made in verilator for cv32e41s.

   SystemVerilog