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  1. fwrisc fwrisc Public

    Forked from Featherweight-IP/fwrisc

    Featherweight RISC-V implementation

    SystemVerilog

  2. AHB-LITE-Verification AHB-LITE-Verification Public

    Verification of AHB-lite bus interface

    SystemVerilog

  3. ara ara Public

    Forked from pulp-platform/ara

    The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

    C

  4. cva6 cva6 Public

    Forked from pulp-platform/cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    C++