Merge branch 'FOSSEE:master' into master

library/SubcircuitLibrary/IC_INA823/IC_INA823-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# lm_741
+#
+DEF lm_741 X 0 40 Y Y 1 F N
+F0 "X" -200 0 60 H V C CNN
+F1 "lm_741" -100 -250 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N
+X off_null 1 -50 400 200 D 50 38 1 1 I
+X inv 2 -550 150 200 R 50 38 1 1 I
+X non_inv 3 -550 -100 200 R 50 38 1 1 I
+X v_neg 4 -150 -450 200 U 50 38 1 1 I
+X off_null 5 50 350 200 D 50 38 1 1 I
+X out 6 550 0 200 L 50 38 1 1 O
+X v_pos 7 -150 450 200 D 50 38 1 1 I
+X NC 8 150 -300 200 U 50 38 1 1 N
+ENDDRAW
+ENDDEF
+#
+#End Library

library/SubcircuitLibrary/IC_INA823/IC_INA823.cir

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+* C:\FOSSEE\eSim\library\SubcircuitLibrary\IC_INA823\IC_INA823.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/19/23 23:14:06
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X2  ? Net-_R1-Pad1_ Net-_U1-Pad1_ V- ? Net-_R1-Pad2_ V+ ? lm_741		
+X1  ? Net-_R2-Pad1_ Net-_U1-Pad4_ V- ? Net-_R2-Pad2_ V+ ? lm_741		
+X3  ? Net-_R4-Pad2_ Net-_R3-Pad2_ V- ? Net-_R6-Pad2_ V+ ? lm_741		
+R2  Net-_R2-Pad1_ Net-_R2-Pad2_ 50k		
+R1  Net-_R1-Pad1_ Net-_R1-Pad2_ 50k		
+R4  Net-_R1-Pad2_ Net-_R4-Pad2_ 50k		
+R3  Net-_R2-Pad2_ Net-_R3-Pad2_ 50k		
+R6  Net-_R4-Pad2_ Net-_R6-Pad2_ 50k		
+R5  Net-_R3-Pad2_ Net-_R5-Pad2_ 50k		
+U1  Net-_U1-Pad1_ Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_U1-Pad4_ V+ Net-_R5-Pad2_ V- Net-_R6-Pad2_ PORT		
+
+.end

library/SubcircuitLibrary/IC_INA823/IC_INA823.cir.out

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+* c:\fossee\esim\library\subcircuitlibrary\ic_ina823\ic_ina823.cir
+
+.include lm_741.sub
+x2 ? net-_r1-pad1_ net-_u1-pad1_ v- ? net-_r1-pad2_ v+ ? lm_741
+x1 ? net-_r2-pad1_ net-_u1-pad4_ v- ? net-_r2-pad2_ v+ ? lm_741
+x3 ? net-_r4-pad2_ net-_r3-pad2_ v- ? net-_r6-pad2_ v+ ? lm_741
+r2  net-_r2-pad1_ net-_r2-pad2_ 50k
+r1  net-_r1-pad1_ net-_r1-pad2_ 50k
+r4  net-_r1-pad2_ net-_r4-pad2_ 50k
+r3  net-_r2-pad2_ net-_r3-pad2_ 50k
+r6  net-_r4-pad2_ net-_r6-pad2_ 50k
+r5  net-_r3-pad2_ net-_r5-pad2_ 50k
+* u1  net-_u1-pad1_ net-_r1-pad1_ net-_r2-pad1_ net-_u1-pad4_ v+ net-_r5-pad2_ v- net-_r6-pad2_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end

library/SubcircuitLibrary/IC_INA823/IC_INA823.pro

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+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri