Implementation of Serial Peripheral Interface (SPI) communication protocol using SystemVerilog and the verification is done using Universal Verification Methodology (UVM). Every design and verification for each component is in a separate file. The wrapper is the SPI design.
• General Knowledge of SPI:
Serial peripheral interface (SPI) is one of the most widely used interfaces between microcontroller and peripheral ICs such as sensors, ADCs, DACs, shift registers, SRAM, and others.
4-wire SPI devices have four signals:
• Clock (SPI CLK, SCLK)
• Chip select (CS)
• main out, subnode in (MOSI)
• main in, subnode out (MISO)
The device that generates the clock signal is called the main. Data transmitted between the main and the subnode is synchronized to the clock generated by the main. SPI devices support much higher clock frequencies compared to I2C interfaces. Users should consult the product data sheet for the clock frequency specification of the SPI interface.
SPI interfaces can have only one main and can have one or multiple subnodes.
The chip select signal from the main is used to select the subnode. This is normally an active low signal and is pulled high to disconnect the subnode from the SPI bus. When multiple subnodes are used, an individual chip selects signal for each subnode is required from the main. In this article, the chip select signal is always an active low signal.
MOSI and MISO are the data lines. MOSI transmits data from the main to the subnode and MISO transmits data from the subnode to the main.
To begin SPI communication, the main must send the clock signal and select the subnode by enabling the CS signal. Usually, chip select is an active low signal; hence, the main must send a logic 0 on this signal to select the subnode. SPI is a full-duplex interface; both main and subnode can send data at the same time via the MOSI and MISO lines respectively. During SPI communication, the data is simultaneously transmitted (shifted out serially onto the MOSI/SDO bus) and received (the data on the bus (MISO/SDI) is sampled or read in). The serial clock edge synchronizes the shifting and sampling of the data. The SPI interface provides the user with flexibility to select the rising or falling edge of the clock to sample and/or shift the data. Please refer to the device data sheet to determine the number of data bits transmitted using the SPI interface.
• About this design:
This is a design of SPI with dual-port RAM.
- RAM:
It has two address ports: one for the read operation and the other for the write operation.
When rx_valid is high, it checks the 2-MSB of rx_data and then:
a) 2’b00: write address operation (it stores the 8-LSB in the write address port).
b) 2’b01: write data operation (it stores the 8-LSB in the address stored in the write address port in the internal memory).
c) 2’b10: read address operation (it stores the 8-LSB in the read address port).
d) 2’b11: read data operation (it reads the data in the address stored in the read address port in the internal memory, out the data to the tx_data port, and assert the tx_valid port. - Slave:
Its design is done using the following FSM:
• UVM Structure:
It has 3 environments: one with active driver and sequencer for the wrapper, the other two with passive drivers and sequencers for the RAM and the Slave.
The sequence is generated for the wrapper.
• Test Methodology:
- Every design has some assertions to test the internal signals and guarantee that everything is working correctly. The assertions are guarded by a macro which is defined before running the testbench.
- The RAM is tested using a SVA file.
- Each scoreboard has a reference model, and the outputs of each design are checked against the outputs of its reference model.
- Each coverage unit has a covergroup to check the functional coverage of its design.
• Test Results:
I. Assertions:
II. Coverage:
III. Transcript:
