⚠ Deprecated: this fork from Verilator would not be updated anymore as version v5.006 fixed the VPI callback VPI: simulation time callbacks should be one-time #2778
⚠ Verilator fork that with VPI callbacks patch required for CoCoTB simulations VPI: simulation time callbacks should be one-time #2778
- patch at branch: v5.002-vpi-callback-patch (
git checkout v5.002-vpi-callback-patch) - cocotb_ver="1.7.1"
- cocotb_bus_ver="v0.1.0" (if using alexforencich/cocotbext-axi, Simulation gets stuck with SIM=verilator 4.106 #35)
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Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files, the "Verilated" code.
These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper file to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators.
Verilator may not be the best choice if you are expecting a full featured replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend Icarus Verilog for classwork.) However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high speed simulation of synthesizable designs containing limited verification constructs, Verilator is the tool for you.
Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a single-thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators).
Verilator has typically similar or better performance versus the closed-source Verilog simulators (Carbon Design Systems Carbonator, Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus Verilator gives you the best cycles/dollar.
For more information:
- Verilator installation and package directory structure
- Verilator manual (HTML), or Verilator manual (PDF)
- Subscribe to verilator announcements
- Verilator forum
- Verilator issues
Verilator is a community project, guided by the CHIPS Alliance under the Linux Foundation.
We appreciate and welcome your contributions in whatever form; please see Contributing to Verilator. Thanks to our Contributors and Sponsors.
Verilator also supports and encourages commercial support models and organizations; please see Verilator Commercial Support.
- GTKwave - Waveform viewer for Verilator traces.
- Icarus Verilog - Icarus is a full featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may.
Verilator is Copyright 2003-2022 by Wilson Snyder. (Report bugs to Verilator Issues.)
Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details.