Welcome to the RPU wiki!

The following information is valid for v1.0 RPU, with csr impid set to "RPU1"

RPU is a 32-bit RISC-V soft core written in VHDL. It passes riscv-compliance for the rv32i, rv32im and rv32Zicsr tests as part of the ArtyS7-RPU-SoC project.

It is a very simple linear 5-stage pipeline which only ever has a single instruction in-flight. There are no internal caches.

The memory interface is a single output address, with command, write enable and size metadata. Input and output data signals are provided, which must be filled/read as sanitized data. I.e, endian byte swizzling must be done prior to being provided to the CPU, and after being read from the CPU in writes.

All ALU execute in a single cycle with the exception of the following:

• MUL/MULH/MULHU/MULHSU: 2 cycles
• DIV/REM/DIVU/REMU: 34 cycles

Memory operation latency varies depending on underlying implementation, however the ArtyS7-RPU-SoC latencies are as follows.

• Fetches have a minimum of 5 cycles latency.
• Loads have a minimum of 2 cycles latency.
• Stores have a minimum of 5 cycles latency.

Machine level vectored interrupt handling is fully supported for misaligned jumps, loads and stores, decoder interrupts (invalid instructions, breakpoints, syscalls), CSR access violations, and external interrupts.

As part of a 100MHz ArtyS7-RPU-SoC, using standard build methodology using Xilinx Vivado 2018.1, the core uses the following resources. No effort has been put into reducing utilization at this time.

• Slice LUTs: 3291
• Slice Reg: 1156
• F7 MUX: 80
• Slices: 1116
• LUT as Logic: 3291
• LUT FlipFlopPairs: 508
• Block RAM Tile: 1
• DSPs: 12