Commits

Commits on Sep 11, 2020

Clarify DooM timedemo score CPU speed
Domipheus
committedSep 11, 2020

Commits on Sep 10, 2020

RPU 1.0
Domipheus
committedSep 10, 2020

Commits on May 17, 2020

Update readme to reflect latest status
Domipheus
committedMay 17, 2020
Core can now boot Zephyr RTOS
Domipheus
committedMay 17, 2020

Commits on Dec 14, 2018

Stores should go though writeback in order for a interrupt check (can be optimized later).
Domipheus
committedDec 14, 2018
Fix bug in which OP decode previously went though the others=> case, which is now solely for invalid instructions. This caused an illegal intruction interrupt on all OP instructions (add,sub) or if…
Domipheus
committedDec 14, 2018

Commits on Nov 21, 2018

RISC-V Machine level Interrupt support first pass.
Domipheus
committedNov 21, 2018

Commits on Nov 16, 2018

Commits on Nov 12, 2018

Start of CSR and interrupt support for machine-mode level operations. No testbenches and the CSR operations are not fixed up yet. Some basic read values are included but as the register write logic…
Domipheus
committedNov 12, 2018

Commits on Sep 17, 2018

Apache 2 license file headers (yes, most of this was written 2 years ago!)
Domipheus
committedSep 17, 2018
Add License
Domipheus
committedSep 17, 2018

Commits on Sep 11, 2018

Rearrange readme and add overview image.
Domipheus
committedSep 11, 2018
Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing.
Domipheus
committedSep 11, 2018
Initial commit
Domipheus
committedSep 11, 2018