device: add wrapper for VGA

perip/vga/vga_top_apb.v

@@ -0,0 +1,23 @@
+module vga_top_apb(
+ input clock,
+ input reset,
+ input [31:0] in_paddr,
+ input in_psel,
+ input in_penable,
+ input [2:0] in_pprot,
+ input in_pwrite,
+ input [31:0] in_pwdata,
+ input [3:0] in_pstrb,
+ output in_pready,
+ output [31:0] in_prdata,
+ output in_pslverr,
+
+ output [7:0] vga_r,
+ output [7:0] vga_g,
+ output [7:0] vga_b,
+ output vga_hsync,
+ output vga_vsync,
+ output vga_valid
+);
+
+endmodule

src/SoC.scala

@@ -33,6 +33,7 @@ class ysyxSoCASIC(implicit p: Parameters) extends LazyModule {
  val luart = LazyModule(new APBUart16550(AddressSet.misaligned(0x10000000, 0x1000)))
  val lgpio = LazyModule(new APBGPIO(AddressSet.misaligned(0x10002000, 0x10)))
  val lkeyboard = LazyModule(new APBKeyboard(AddressSet.misaligned(0x10011000, 0x8)))
+ val lvga = LazyModule(new APBVGA(AddressSet.misaligned(0x21000000, 0x200000)))
  val lspi = LazyModule(new APBSPI(
  AddressSet.misaligned(0x10001000, 0x1000) ++ // SPI controller
  AddressSet.misaligned(0x30000000, 0x10000000) // XIP flash
@@ -42,7 +43,7 @@ class ysyxSoCASIC(implicit p: Parameters) extends LazyModule {
  val sramNode = AXI4RAM(AddressSet.misaligned(0x0f000000, 0x2000).head, false, true, 8, None, Nil, false)
  val lsdram = LazyModule(new APBSDRAM(AddressSet.misaligned(0xa0000000L, 0x2000000)))
 
- List(lspi.node, luart.node, lpsram.node, lsdram.node, lgpio.node, lkeyboard.node).map(_ := apbxbar)
+ List(lspi.node, luart.node, lpsram.node, lsdram.node, lgpio.node, lkeyboard.node, lvga.node).map(_ := apbxbar)
  List(apbxbar := AXI4ToAPB(), lmrom.node, sramNode).map(_ := xbar)
  if (Config.hasChipLink) chiplinkNode.get := xbar
  xbar := cpu.masterNode
@@ -78,12 +79,14 @@ class ysyxSoCASIC(implicit p: Parameters) extends LazyModule {
  val sdram = IO(chiselTypeOf(lsdram.module.sdram_bundle))
  val gpio = IO(chiselTypeOf(lgpio.module.gpio_bundle))
  val ps2 = IO(chiselTypeOf(lkeyboard.module.ps2_bundle))
+ val vga = IO(chiselTypeOf(lvga.module.vga_bundle))
  uart <> luart.module.uart
  spi <> lspi.module.spi_bundle
  psram <> lpsram.module.qspi_bundle
  sdram <> lsdram.module.sdram_bundle
  gpio <> lgpio.module.gpio_bundle
  ps2 <> lkeyboard.module.ps2_bundle
+ vga <> lvga.module.vga_bundle
  }
 }
 
@@ -136,8 +139,10 @@ class ysyxSoCFull(implicit p: Parameters) extends LazyModule {
  val externalPins = IO(new Bundle{
  val gpio = chiselTypeOf(masic.gpio)
  val ps2 = chiselTypeOf(masic.ps2)
+ val vga = chiselTypeOf(masic.vga)
  })
  externalPins.gpio <> masic.gpio
  externalPins.ps2 <> masic.ps2
+ externalPins.vga <> masic.vga
  }
 }

src/device/VGA.scala

@@ -0,0 +1,55 @@
+package ysyx
+
+import chisel3._
+import chisel3.util._
+
+import freechips.rocketchip.amba.apb._
+import org.chipsalliance.cde.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util._
+
+class VGAIO extends Bundle {
+ val r = Output(UInt(8.W))
+ val g = Output(UInt(8.W))
+ val b = Output(UInt(8.W))
+ val hsync = Output(Bool())
+ val vsync = Output(Bool())
+ val valid = Output(Bool())
+}
+
+class VGACtrlIO extends Bundle {
+ val clock = Input(Clock())
+ val reset = Input(Bool())
+ val in = Flipped(new APBBundle(APBBundleParameters(addrBits = 32, dataBits = 32)))
+ val vga = new VGAIO
+}
+
+class vga_top_apb extends BlackBox {
+ val io = IO(new VGACtrlIO)
+}
+
+class vgaChisel extends Module {
+ val io = IO(new VGACtrlIO)
+}
+
+class APBVGA(address: Seq[AddressSet])(implicit p: Parameters) extends LazyModule {
+ val node = APBSlaveNode(Seq(APBSlavePortParameters(
+ Seq(APBSlaveParameters(
+ address = address,
+ executable = true,
+ supportsRead = true,
+ supportsWrite = true)),
+ beatBytes = 4)))
+
+ lazy val module = new Impl
+ class Impl extends LazyModuleImp(this) {
+ val (in, _) = node.in(0)
+ val vga_bundle = IO(new VGAIO)
+
+ val mvga = Module(new vga_top_apb)
+ mvga.io.clock := clock
+ mvga.io.reset := reset
+ mvga.io.in <> in
+ vga_bundle <> mvga.io.vga
+ }
+}