amba: add wrapper for APBDelayer

perip/amba/apb_delayer.v

@@ -0,0 +1,38 @@
+module apb_delayer(
+ input clock,
+ input reset,
+ input [31:0] in_paddr,
+ input in_psel,
+ input in_penable,
+ input [2:0] in_pprot,
+ input in_pwrite,
+ input [31:0] in_pwdata,
+ input [3:0] in_pstrb,
+ output in_pready,
+ output [31:0] in_prdata,
+ output in_pslverr,
+
+ output [31:0] out_paddr,
+ output out_psel,
+ output out_penable,
+ output [2:0] out_pprot,
+ output out_pwrite,
+ output [31:0] out_pwdata,
+ output [3:0] out_pstrb,
+ input out_pready,
+ input [31:0] out_prdata,
+ input out_pslverr
+);
+
+ assign out_paddr = in_paddr;
+ assign out_psel = in_psel;
+ assign out_penable = in_penable;
+ assign out_pprot = in_pprot;
+ assign out_pwrite = in_pwrite;
+ assign out_pwdata = in_pwdata;
+ assign out_pstrb = in_pstrb;
+ assign in_pready = out_pready;
+ assign in_prdata = out_prdata;
+ assign in_pslverr = out_pslverr;
+
+endmodule

src/SoC.scala

@@ -44,7 +44,7 @@ class ysyxSoCASIC(implicit p: Parameters) extends LazyModule {
  val lsdram = LazyModule(new APBSDRAM(AddressSet.misaligned(0xa0000000L, 0x2000000)))
 
  List(lspi.node, luart.node, lpsram.node, lsdram.node, lgpio.node, lkeyboard.node, lvga.node).map(_ := apbxbar)
- List(apbxbar := AXI4ToAPB(), lmrom.node, sramNode).map(_ := xbar)
+ List(apbxbar := APBDelayer() := AXI4ToAPB(), lmrom.node, sramNode).map(_ := xbar)
  if (Config.hasChipLink) chiplinkNode.get := xbar
  xbar := cpu.masterNode
 

src/amba/APBDelayer.scala

@@ -0,0 +1,48 @@
+package ysyx
+
+import chisel3._
+import chisel3.util._
+
+import org.chipsalliance.cde.config.Parameters
+import freechips.rocketchip.amba._
+import freechips.rocketchip.amba.apb._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util._
+
+class APBDelayerIO extends Bundle {
+ val clock = Input(Clock())
+ val reset = Input(Reset())
+ val in = Flipped(new APBBundle(APBBundleParameters(addrBits = 32, dataBits = 32)))
+ val out = new APBBundle(APBBundleParameters(addrBits = 32, dataBits = 32))
+}
+
+class apb_delayer extends BlackBox {
+ val io = IO(new APBDelayerIO)
+}
+
+class APBDelayerChisel extends Module {
+ val io = IO(new APBDelayerIO)
+ io.out <> io.in
+}
+
+class APBDelayerWrapper(implicit p: Parameters) extends LazyModule {
+ val node = APBIdentityNode()
+
+ lazy val module = new Impl
+ class Impl extends LazyModuleImp(this) {
+ (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
+ val delayer = Module(new apb_delayer)
+ delayer.io.clock := clock
+ delayer.io.reset := reset
+ delayer.io.in <> in
+ out <> delayer.io.out
+ }
+ }
+}
+
+object APBDelayer {
+ def apply()(implicit p: Parameters): APBNode = {
+ val apbdelay = LazyModule(new APBDelayerWrapper)
+ apbdelay.node
+ }
+}