support sdram byte extension

src/SoC.scala

@@ -43,7 +43,7 @@ class ysyxSoCASIC(implicit p: Parameters) extends LazyModule {
  val lmrom = LazyModule(new AXI4MROM(AddressSet.misaligned(0x20000000, 0x1000)))
  val sramNode = AXI4RAM(AddressSet.misaligned(0x0f000000, 0x2000).head, false, true, 8, None, Nil, false)
 
- val sdramAddressSet = AddressSet.misaligned(0xa0000000L, 0x2000000) // 32MB
+ val sdramAddressSet = AddressSet.misaligned(0xa0000000L, 0x2000000*4) //0x2000000 is 32MB, one sdram is 32MB, bit and byte extension to 128MB
  val lsdram_apb = if (!Config.sdramUseAXI) Some(LazyModule(new APBSDRAM (sdramAddressSet))) else None
  val lsdram_axi = if ( Config.sdramUseAXI) Some(LazyModule(new AXI4SDRAM(sdramAddressSet))) else None
 
@@ -152,13 +152,15 @@ class ysyxSoCFull(implicit p: Parameters) extends LazyModule {
 
  val sdram0 = Module(new sdram)
  val sdram1 = Module(new sdram)
+ val sdram2 = Module(new sdram)
+ val sdram3 = Module(new sdram)
  // val m2s = Module(new sdram_m2s)
  // m2s.io.in <> masic.sdram
  // sdram0.io <> m2s.io.out0
  // sdram1.io <> m2s.io.out1
  sdram0.io.clk := masic.sdram.clk
  sdram0.io.cke := masic.sdram.cke
- sdram0.io.cs := masic.sdram.cs
+ sdram0.io.cs := masic.sdram.cs0
  sdram0.io.ras := masic.sdram.ras
  sdram0.io.cas := masic.sdram.cas
  sdram0.io.we := masic.sdram.we
@@ -169,7 +171,7 @@ class ysyxSoCFull(implicit p: Parameters) extends LazyModule {
 
  sdram1.io.clk := masic.sdram.clk
  sdram1.io.cke := masic.sdram.cke
- sdram1.io.cs := masic.sdram.cs
+ sdram1.io.cs := masic.sdram.cs0
  sdram1.io.ras := masic.sdram.ras
  sdram1.io.cas := masic.sdram.cas
  sdram1.io.we := masic.sdram.we
@@ -178,6 +180,29 @@ class ysyxSoCFull(implicit p: Parameters) extends LazyModule {
  sdram1.io.dqm := masic.sdram.dqm(3, 2)
  sdram1.io.dq <> masic.sdram.dq1
 
+ sdram2.io.clk := masic.sdram.clk
+ sdram2.io.cke := masic.sdram.cke
+ sdram2.io.cs := masic.sdram.cs1
+ sdram2.io.ras := masic.sdram.ras
+ sdram2.io.cas := masic.sdram.cas
+ sdram2.io.we := masic.sdram.we
+ sdram2.io.a := masic.sdram.a
+ sdram2.io.ba := masic.sdram.ba
+ // sdram2.io.dqm := masic.sdram.dqm(3, 2) // bugs here!
+ sdram2.io.dqm := masic.sdram.dqm(1, 0)
+ sdram2.io.dq <> masic.sdram.dq2
+
+ sdram3.io.clk := masic.sdram.clk
+ sdram3.io.cke := masic.sdram.cke
+ sdram3.io.cs := masic.sdram.cs1
+ sdram3.io.ras := masic.sdram.ras
+ sdram3.io.cas := masic.sdram.cas
+ sdram3.io.we := masic.sdram.we
+ sdram3.io.a := masic.sdram.a
+ sdram3.io.ba := masic.sdram.ba
+ sdram3.io.dqm := masic.sdram.dqm(3, 2)
+ sdram3.io.dq <> masic.sdram.dq3
+
  val externalPins = IO(new Bundle{
  // val gpio = chiselTypeOf(masic.gpio)
  // val ps2 = chiselTypeOf(masic.ps2)

src/device/SDRAM.scala

@@ -26,7 +26,8 @@ class SDRAMIO extends Bundle {
 class SDRAMIO_master extends Bundle {
  val clk = Output(Bool())
  val cke = Output(Bool())
- val cs = Output(Bool())
+ val cs0 = Output(Bool()) // for sdram 0, 1
+ val cs1 = Output(Bool()) // for sdram 2, 3
  val ras = Output(Bool())
  val cas = Output(Bool())
  val we = Output(Bool())
@@ -36,6 +37,8 @@ class SDRAMIO_master extends Bundle {
  // val dq = Analog(32.W)
  val dq0 = Analog(16.W)
  val dq1 = Analog(16.W)
+ val dq2 = Analog(16.W)
+ val dq3 = Analog(16.W)
 }
 
 class SDRAMIO_slave extends Bundle {
@@ -52,37 +55,37 @@ class SDRAMIO_slave extends Bundle {
 }
 
 // connect master to slave
-class sdram_m2s extends Module {
- val io = IO(new Bundle {
- val in = Flipped(new SDRAMIO_master)
- // val out = Vec(2, new SDRAMIO_slave)
- val out0 = new SDRAMIO_slave
- val out1 = new SDRAMIO_slave
- })
-
- // 0, 1 is bit extension
- io.out0.clk := io.in.clk
- io.out0.cke := io.in.cke
- io.out0.cs := io.in.cs
- io.out0.ras := io.in.ras
- io.out0.cas := io.in.cas
- io.out0.we := io.in.we
- io.out0.a := io.in.a
- io.out0.ba := io.in.ba
- io.out0.dqm := io.in.dqm(1, 0)
- io.out0.dq <> io.in.dq0
-
- io.out1.clk := io.in.clk
- io.out1.cke := io.in.cke
- io.out1.cs := io.in.cs
- io.out1.ras := io.in.ras
- io.out1.cas := io.in.cas
- io.out1.we := io.in.we
- io.out1.a := io.in.a
- io.out1.ba := io.in.ba
- io.out1.dqm := io.in.dqm(3, 2)
- io.out1.dq <> io.in.dq1
-}
+// class sdram_m2s extends Module {
+//  val io = IO(new Bundle {
+//  val in = Flipped(new SDRAMIO_master)
+//  // val out = Vec(2, new SDRAMIO_slave)
+//  val out0 = new SDRAMIO_slave
+//  val out1 = new SDRAMIO_slave
+//  })
+// 
+//  // 0, 1 is bit extension
+//  io.out0.clk := io.in.clk
+//  io.out0.cke := io.in.cke
+//  io.out0.cs := io.in.cs
+//  io.out0.ras := io.in.ras
+//  io.out0.cas := io.in.cas
+//  io.out0.we := io.in.we
+//  io.out0.a := io.in.a
+//  io.out0.ba := io.in.ba
+//  io.out0.dqm := io.in.dqm(1, 0)
+//  io.out0.dq <> io.in.dq0
+// 
+//  io.out1.clk := io.in.clk
+//  io.out1.cke := io.in.cke
+//  io.out1.cs := io.in.cs
+//  io.out1.ras := io.in.ras
+//  io.out1.cas := io.in.cas
+//  io.out1.we := io.in.we
+//  io.out1.a := io.in.a
+//  io.out1.ba := io.in.ba
+//  io.out1.dqm := io.in.dqm(3, 2)
+//  io.out1.dq <> io.in.dq1
+// }
 
 class sdram_top_axi extends BlackBox {
  val io = IO(new Bundle {