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1. instruction_cache instruction_cache Public

   Four-way set associative blocking cache with 16 sets and a block size of 16 words per block. Best-case miss penalty of 5 cycles. Physical Design and Static Timing Analysis performed using OpenLane …

   Verilog 3

2. veritrace veritrace Public

   A tool used to enable static signal tracing and exploration of designs which are written in (system)verilog.

   HTML

3. triple-ported-memory triple-ported-memory Public

   A pipelined multi-banked memory module with a dynamic-priority arbitration scheme to resolve bank conflicts. 8KB Total Capacity with Physical Design performed using OpenLane RTL-to-GDS flow on SKY1…

   Verilog 2

4. 16_bit_microprocessor 16_bit_microprocessor Public

   A 16 bit multicycle microprocessor modeled using SystemVerilog and developed using Xilinx Vivado.

   SystemVerilog

5. PhotoCrypt PhotoCrypt Public

   An app that encrypts photos :)

   C++ 2

6. Optimal-Position-Algorithm Optimal-Position-Algorithm Public

   An attempt to develop an algorithm that optimizes the location of objects (called servers) that interact with other objects (called nodes) within a predefined range.

   Jupyter Notebook