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1. APIR-DSP APIR-DSP Public

   The FPT'21 paper "APIR-DSP" source code.

   Verilog 5

2. UPTRA UPTRA Public

   UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization

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3. 32-bit-Multiplier 32-bit-Multiplier Public

   A 32-bit Baugh-Wooley multiplier with carry-select add.

   Verilog 2

4. HETA HETA Public

   HETA: A Heterogeneous Temporal CGRA Modeling and Bayesian-based Optimization

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5. aha aha Public

   Forked from StanfordAHA/aha

   https://aha.readthedocs.io/en/latest/

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6. pillars pillars Public

   Forked from pku-dasys/pillars

   An integrated CGRA design framework

   Scala 1