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PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,095 749 Updated Jun 27, 2024

CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.

Python 102 13 Updated Oct 15, 2024

Xidian University TeX Suite 西安电子科技大学LaTeX套装

TeX 704 71 Updated Mar 23, 2023

全国各省市停贷通知汇总

HTML 20,344 2,133 Updated Jul 13, 2024

lists of most popular repositories for most favoured programming languages (according to StackOverflow)

Python 75 22 Updated Oct 9, 2020

The Ultra-Low Power RISC-V Core

Verilog 1,238 341 Updated Oct 9, 2024

All the files for ZX-Uno project repository

VHDL 112 31 Updated Jul 30, 2024

OpenTitan: Open source silicon root of trust

SystemVerilog 2,554 761 Updated Oct 16, 2024

🌳 The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation tool…

JavaScript 98 15 Updated Sep 17, 2022

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,102 282 Updated Oct 11, 2024

程序员延寿指南 | A programmer's guide to live longer

29,877 2,093 Updated Jan 30, 2024

ZC RISCV CORE

Verilog 13 1 Updated Dec 19, 2019

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,617 1,010 Updated Mar 24, 2021
Jupyter Notebook 1,618 520 Updated Feb 16, 2023

基于Typecho评论推送服务

PHP 116 19 Updated Dec 13, 2021