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DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Sep 11, 2022

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Oct 10, 2024

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Apr 8, 2024

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Apr 8, 2024

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Apr 8, 2024

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Apr 8, 2024

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 2 Updated Jun 23, 2022

Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

Verilog 1 Updated Aug 11, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.

Verilog 1 Updated Jan 15, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022

YM2149 / AY-3-8910 Programmable Sound Generator. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital audio out, and built in floa…

SystemVerilog 1 Updated Sep 8, 2022

YM2149 / AY-3-8910 Programmable Sound Generator in SystemVerilog and Verilog. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital…

SystemVerilog 5 2 Updated Sep 8, 2022

A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.

SystemVerilog 6 Updated Jun 26, 2023

Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

Verilog 14 1 Updated Aug 11, 2022

Verilog clone of YM2149

Verilog 41 9 Updated Apr 2, 2024
Verilog 10 1 Updated Oct 20, 2015

YM-2149 / AY-3-8910 Complex Sound Generator FPGA core.

VHDL 21 1 Updated Jan 4, 2023

Minimig for SoCkit (MiSTer)

Verilog 1 Updated Jun 12, 2022

FPGA based USB 2.0 high speed audio interface featuring multiple optical ADAT inputs and outputs

Python 1 Updated Jun 12, 2022

FPGA based USB 2.0 high speed audio interface featuring multiple optical ADAT inputs and outputs

Python 143 17 Updated Sep 17, 2024

Minimig for SoCkit (MiSTer)

Verilog 1 Updated Jun 12, 2022

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

SystemVerilog 1 Updated Jun 23, 2022
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