Add support for some clock and reset pragmas to Classic #624
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Move existing Pragmas.bs test there. Add test cases for gate_input_clocks and clock_family pragmas in Classic.
…x pragmas. Add a testcase for the prefix pragmas. Check for duplicate prefix pragmas in PragmaCheck because, unlike BSV, the Classic parser lets duplicate pragmas through. Add testcases for the duplicate pragma check.
| {-# synthesize mkClockFamily { | ||
| gate_input_clocks = { default_clock }, | ||
| clock_family = { default_clock, ungated } } #-} | ||
| mkClockFamily :: (IsModule m mType) => Clock -> m Ticked |
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It's minor, but do you want to name the module with sys instead of mk? It would require also renaming the expected Verilog file? (And the same for NoClockFamily.bs.)
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I thought we mainly used sys for top-level testbenches and the like. I used mk here because I made a component meant to be instantiated in something larger.
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I will merge the PR as it is now; I don't want to keep making work for you. But to answer your question: I guess I don't see the difference between this module named mk and all the other test files with modules named sys. I don't see how either is more or less a submodule versus a top module. I guess it really only matters for commands that expect a top-module (like test_c_veri_bs) and here we're just using compile_verilog_pass, but I tend to use the same structure even when I'm not using test_*, of making the top (or only) module in the file be named with sys, which is why I found this use of mk odd (plus the inconsistency with the other files, which are also not using test_*, but still named sys).
…ibute error message. Check for the correct pragma in the compiler output for the error tests.
…y one error in the file.
GateUnknownClock and UnknownClockFamily tests.
This includes support for gate_input_clocks, clock_family, clock_prefix, reset_prefix and gate_prefix. Partially addresses #224 and fixes #616