This repository contains various peripheral drivers written in Verilog for open-source ICE40 FPGAs. iCESuger nano FPGA ships with several PMOD accessories. This repository contains Verilog IPs to work with them.
LCD driver is configured for ICESugar nano default clock rate of 12MHz and this driver can save your SPI pins for SPI stuff.
Build Yosys toolchain is required to build the binary files. For this, you can use the following docker container with all the dependencies
Follow the steps to build using the docker environment. (You should have the docker daemon installed on your system)
- Clone the repository
git clone https://github.com/Archfx/ice40lib
- Pull the docker image from docker-hub
docker pull archfx/ice40tools
- Set the expected location to mount with the container
export LOC=/ice40lib
- Run the Docker image
docker run -t -p 6080:6080 -v "${PWD}/:/$LOC" -w /$LOC --name ice40tools archfx/ice40tools
This will open up a browser window with
- Connect to the docker image
docker exec -it ice40tools /bin/bash
- Compile the design and upload
Note change the --pl1k parameter with the chip model that you have. iCESugar Nano uses ice40LP1k-CM36 chip
cd ice40/examples/blinky
yosys -p 'synth_ice40 -top blinky -json blinky.json' blinky.v # synthesize into blinky.json
nextpnr-ice40 --lp1k --json blinky.json --pcf blinky.pcf --asc blinky.asc --package cm36 # run place and route
icepack blinky.asc blinky.bin # generate binary bitstream file
iceprog blinky.bin