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AnoushkaTripathi/README.md

Hi there, I'm Anoushka Tripathi! πŸ‘‹

Welcome to my GitHub profile! I'm a passionate VLSI engineer with a love for designing and optimizing digital circuits and systems.

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πŸ› οΈ Technologies & Tools

FPGA VIVADO HLS Machine Learning Verilog OpenLane RISC-V Python Git C C++

πŸ“ˆ GitHub Stats

Top Langs

πŸš€ Projects

πŸ’¬ Get in Touch

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  1. NIELIT-INTERNSHIP-ON-HLS-PROGRAMMING NIELIT-INTERNSHIP-ON-HLS-PROGRAMMING Public

    In this VLSI design course, we explored topics such as HLS programming, combination circuits, sequential circuits, and a capstone project. From high-level synthesis to hands-on application, this co…

    C++ 5

  2. Nano_Satellite_Design Nano_Satellite_Design Public

    Jupyter Notebook

  3. VSD_SQUADRON_MINI_RISCV_RESEARCH_INTERNSHIP VSD_SQUADRON_MINI_RISCV_RESEARCH_INTERNSHIP Public

    A hands-on program focusing on RISC-V development, including tasks from software setup to creating and demonstrating practical application using RISC V processor.

    C 2

  4. adarshnagrikar14/jeevayu-gsc-22 adarshnagrikar14/jeevayu-gsc-22 Public

    Jeevayu is a team project for Google solution challenge 2022.

    Dart 2

  5. NASSCOM-VSD-SoC-design-Program NASSCOM-VSD-SoC-design-Program Public

    In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)

    7 1

  6. Efficient-Hardware-Software-Codesign-for-accelerating-Vision-Transformer-ViT-Inference Efficient-Hardware-Software-Codesign-for-accelerating-Vision-Transformer-ViT-Inference Public

    This project aims to optimize the inference of Vision Transformers (ViTs) on edge IoT devices using a hybrid hardware-software co-design approach.

    SystemVerilog 2