Resource efficient UPnP/DLNA renderer, optimal for Raspberry Pi, CuBox or a general MediaServer. Fork of GMediaRenderer to add some features to make it usable.

Resource efficient UPnP/DLNA renderer, optimal for Raspberry Pi, CuBox, CubieBoard or a general MediaServer. Fork of gmrender-resurrect to make use of OpenHome

OpenHome Audio and Video Renderer

ohPlayer is a full featured OpenHome media renderer licenced under an MIT licence

OpenHome audio pipeline

OpenHome Networking (ohNet) is a modern, cross platform, multi-language UPnP stack

Delta-Sigma ADC&DAC by FPGA

Vitis In-Depth Tutorials

Circuit IR Compilers and Tools

2-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.

HDL code for a DDS (direct digital synthesizer) with AXI stream interface

FPGA samples

HTLAB.NET Efinix Download Cable

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

A SystemVerilog Language Server

VUnit is a unit testing framework for VHDL/SystemVerilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

UVM 1.2 port to Python

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端…

An Open-source FPGA IP Generator

HDL support for VS Code

Open source implementation of a Verilog formatter

SystemVerilog Tutorial

VHDL 2008/93/87 simulator

A C library for reading and writing sound files containing sampled audio data.

Yosys Open SYnthesis Suite

SACD decoder (shared library)

Converts SACD image files, Philips DSDIFF and Sony DSF files to 24-bit high resolution wave files. Handles both DST and DSD streams. https://launchpad.net/sacd