Improve the startup code on the STM32F070 #4525
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This reduces the number of loads inside of the .data copy loop by 3 by using one more register. It should work on any STM32 with at least 5 general-purpose registers. If only 4 are available, then 1 load could still be removed from the original implementation.
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retest uvisor |
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I don't have the ability to do that, nor can I even see the details |
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@fahhem Hello - have you developed this code from scratch in the context of MBED or has this already been exercised before in another context ? |
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I first used it in my custom board with the same chip as the nucleo f070rb
board. It's working for me and I figured it would be useful to upstream it.
It seems the original version was developed for a chip with only 4
registers available and was copied to bigger chips without redesign?
…On Jun 13, 2017 12:12 AM, "Laurent Meunier" ***@***.***> wrote:
@fahhem <https://github.com/fahhem> Hello - have you developed this code
from scratch in the context of MBED or has this already been exercised
before in another context ?
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ST_INTERNAL_REF 34824 |
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@bcostm Will you be updating this in the ST SDK? Should we close this PR? |
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We are going to launch some tests first and we'll let you know if ok to merge. |
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All tests are OK |
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Glad I could help! |
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CLA checked, signed ;) Waiting for CI |
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/morph test |
Result: FAILUREYour command has finished executing! Here's what you wrote!
OutputTest failed! |
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That looks like it failed due to a totally untouched processor timing out, so it seems like it's just flaky? https://mbedosci.cloudapp.net/results/pr/4525/645/FAIL/NCS36510/IAR/test_report_NCS36510-IAR.html |
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/morph test |
Result: FAILUREYour command has finished executing! Here's what you wrote!
OutputTest failed! |
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Seems like it's another different board that's failing. Is morph normally this flaky? |
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/morph test |
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Ah, we limit the users who can trigger our CI. We don't want it DDOSed after all. Let me get that for you. /morph test |
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Is it normal for the CI to be this flaky? |
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Nope. We just merged a few robustness improvements for the CI. I think this run should be more stable. |
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retest uvisor |
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It failed to update the status :( |
Result: SUCCESSYour command has finished executing! Here's what you wrote!
OutputAll builds and test passed! |
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Looks like ram usage went up since the last release for stm32 boards, but not just this one. |
Can you elaborate? |
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retest uvisor |
Description
This reduces the number of loads inside of the .data copy loop by 3 by using one more register. It should work on any STM32 with at least 5 general-purpose registers. If only 4 are available, then 1 load could still be removed from the original implementation.
Status
READY
Migrations
NO
Steps to test or reproduce
Run any program with a non-empty
.datasection (globals, for instance).