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STM32WL: fix MBED_CONF_STM32WL_LORA_DRIVER_SLEEP_MODE option #15322

Merged
merged 1 commit into from
Aug 24, 2022
Merged

STM32WL: fix MBED_CONF_STM32WL_LORA_DRIVER_SLEEP_MODE option #15322

merged 1 commit into from
Aug 24, 2022

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jeromecoutant
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Summary of changes

Fix #15314

If "stm32wl-lora-driver.sleep-mode" was set to 1, build was failing

Warning: Lora application not tested

@chrissnow @hallard

Impact of changes

Migration actions required

Documentation

Pull request type 

[x] Patch update (Bug fix / Target update / Docs update / Test update / Refactor)
[] Feature update (New feature / Functionality change / New API)
[] Major update (Breaking change E.g. Return code change / API behaviour change)

Test results 

[] No Tests required for this change (E.g docs only update)
[x] Covered by existing mbed-os tests (Greentea or Unittest)
[] Tests / results supplied as part of this PR

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@hallard
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hallard commented Aug 18, 2022

Shouldn't this line out of the #ifdef state? because if it compile, it just does nothing (or may be default sleep state is set to 0) but it's hard to understand

  write_opmode_command(RADIO_SET_SLEEP, &sleep_state, 1);

@hallard
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hallard commented Aug 18, 2022 •
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ah ah has been changed while I was writing, now sounds good to me, and win approx 0.5uA is always a good thing, I really need to test this option

@ciarmcom ciarmcom added the release-type: patch Indentifies a PR as containing just a patch label Aug 18, 2022
@ciarmcom ciarmcom requested a review from a team August 18, 2022 13:00
@ciarmcom
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@jeromecoutant, thank you for your changes.
@ARMmbed/mbed-os-maintainers please review.

@0xc0170
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0xc0170 commented Aug 23, 2022

CI started

@mergify mergify bot added needs: CI and removed needs: review labels Aug 23, 2022
@mbed-ci
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mbed-ci commented Aug 23, 2022

Jenkins CI Test : ✔️ SUCCESS

Build Number: 1 | 🔒 Jenkins CI Job | 🌐 Logs & Artifacts

CLICK for Detailed Summary

jobs Status
jenkins-ci/mbed-os-ci_build-cloud-example-ARM ✔️
jenkins-ci/mbed-os-ci_build-greentea-ARM ✔️
jenkins-ci/mbed-os-ci_build-cloud-example-GCC_ARM ✔️
jenkins-ci/mbed-os-ci_unittests ✔️
jenkins-ci/mbed-os-ci_build-example-ARM ✔️
jenkins-ci/mbed-os-ci_build-greentea-GCC_ARM ✔️
jenkins-ci/mbed-os-ci_build-example-GCC_ARM ✔️
jenkins-ci/mbed-os-ci_greentea-test ✔️

@0xc0170 0xc0170 merged commit c9a3db5 into ARMmbed:master Aug 24, 2022
@mergify mergify bot removed the ready for merge label Aug 24, 2022
@chrissnow
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@jeromecoutant apologies this has takes so long to get around to testing.
unfortunately It seems to break the join process as below.

"stm32wl-lora-driver.sleep-mode": 1 

Mbed LoRaWANStack initialized

 CONFIRMED message retries : 3

 Adaptive data  rate (ADR) - Enabled

 Connection - In Progress ...

 OTAA Failed - Check Keys

 Mbed LoRaWANStack initialized

 CONFIRMED message retries : 3

 Adaptive data  rate (ADR) - Enabled

 Connection - In Progress ...
[DBG ][LSTK]: Initializing MAC layer

 Mbed LoRaWANStack initialized

 CONFIRMED message retries : 3

 Adaptive data  rate (ADR) - Enabled
[DBG ][LSTK]: Initiating OTAA
[DBG ][LSTK]: Sending Join Request ...
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: TX: Channel=2, TX DR=5, RX1 DR=5

 Connection - In Progress ...
[DBG ][LSTK]: Transmission completed

[DBG ][LSTK]: Initializing MAC layer

 Mbed LoRaWANStack initialized

 CONFIRMED message retries : 3

 Adaptive data  rate (ADR) - Enabled
[DBG ][LSTK]: Initiating OTAA
[DBG ][LSTK]: Sending Join Request ...
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: TX: Channel=1, TX DR=5, RX1 DR=5

 Connection - In Progress ...
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868300000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: TX: Channel=2, TX DR=4, RX1 DR=4
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868500000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 4912 ms
[DBG ][LMAC]: TX: Channel=1, TX DR=3, RX1 DR=3
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868300000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 14424 ms
[DBG ][LMAC]: TX: Channel=2, TX DR=2, RX1 DR=2
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868500000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 30273 ms
[DBG ][LMAC]: TX: Channel=2, TX DR=1, RX1 DR=1
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868500000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 75182 ms
[DBG ][LMAC]: TX: Channel=2, TX DR=0, RX1 DR=0
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868500000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 140738 ms
[DBG ][LMAC]: TX: Channel=1, TX DR=5, RX1 DR=5
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868300000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: TX: Channel=0, TX DR=4, RX1 DR=4
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868100000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 4805 ms
[DBG ][LMAC]: TX: Channel=0, TX DR=3, RX1 DR=3
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868100000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 14304 ms
[DBG ][LMAC]: TX: Channel=2, TX DR=2, RX1 DR=2
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868500000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 30593 ms
[DBG ][LMAC]: TX: Channel=2, TX DR=1, RX1 DR=1
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868500000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: DC enforced: Transmitting in 75417 ms
[DBG ][LMAC]: TX: Channel=1, TX DR=0, RX1 DR=0
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868300000
[DBG ][LMAC]: RX2 slot open, Freq = 869525000

 OTAA Failed - Check Keys

vs
"stm32wl-lora-driver.sleep-mode": 0 

Mbed LoRaWANStack initialized

 CONFIRMED message retries : 3

 Adaptive data  rate (ADR) - Enabled
[DBG ][LSTK]: Initiating OTAA
[DBG ][LSTK]: Sending Join Request ...
[DBG ][LMAC]: Frame prepared to send at port 0
[DBG ][LMAC]: TX: Channel=0, TX DR=5, RX1 DR=5

 Connection - In Progress ...
[DBG ][LSTK]: Transmission completed
[DBG ][LMAC]: RX1 slot open, Freq = 868100000
[DBG ][LSTK]: OTAA Connection OK!

 Connection - Successful

@jeromecoutant jeromecoutant deleted the PR_WL_SLEEP branch November 24, 2022 14:44
@mbedmain mbedmain removed release-type: patch Indentifies a PR as containing just a patch Release-pending labels Feb 28, 2023
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STM32WL - LoRa sleep-mode
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@jeromecoutant @hallard @ciarmcom @0xc0170 @mbed-ci @chrissnow @saheerb @mbedmain