Commits

Commits on Dec 22, 2021

Update README.md
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committedDec 22, 2021
Merge branch 'efabless:main' into main
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committedDec 22, 2021

Commits on Dec 16, 2021

clean up
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committedDec 16, 2021

Commits on Dec 15, 2021

Merge pull request #1 from ankursharma129/main
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committedDec 15, 2021

Commits on Dec 14, 2021

32x32 pixel array sch, need busses
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committedDec 14, 2021
pixel sch and sym for 4x4
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committedDec 14, 2021

Commits on Dec 11, 2021

reduced inv size 2x4 xschem
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committedDec 11, 2021
spice files for netgen
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committedDec 11, 2021
2x4 0/1 ports reduced, inverter_customized reinstanced
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committedDec 11, 2021
deleted duplicate ports on 2x4 0 and 1 cell
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committedDec 11, 2021
reduced default inv and tran gate sizes to 1u/0.18u, but previously instanced gates would retain their size
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committedDec 11, 2021
clkgen working ok for phi1, phi2, div2, and reset. cclk is bad.
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committedDec 11, 2021

Commits on Dec 10, 2021

weak inverters for phi1 phi2 generation
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committedDec 10, 2021
inv and transmission gate parameterized, pmos width defaulted to 3u for tran gate
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committedDec 10, 2021

Commits on Dec 9, 2021

decoder netlist errors cleared
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committedDec 9, 2021
reduced decorder transistor L to 0.15u, updated 0 cell, wired decoder, peripheral cells have errors
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committedDec 9, 2021

Commits on Dec 8, 2021

Merge branch 'main' of https://github.com/3x10e8/cochlea_sky130 into main
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committedDec 8, 2021
wavelet channel and last cap thresholding
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committedDec 8, 2021
i-q wavelet channel added
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committedDec 8, 2021
pmos was flipped on transmission gate, fixed
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committedDec 8, 2021
bin ctr not working
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committedDec 8, 2021

Commits on Dec 7, 2021

std cell t flip flop added
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committedDec 7, 2021
trying std cell for lp xor2, might have bad connections
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committedDec 7, 2021
async comparator and test bench
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committedDec 7, 2021

Commits on Dec 5, 2021

comparator first stage testing
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committedDec 5, 2021
comparator output branches swapped
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committedDec 5, 2021
Siddharth comparator, needs tuning
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committedDec 5, 2021

Commits on Dec 4, 2021

single-ended 16 switch-cap test bench
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committedDec 4, 2021
corrected params in switchcap sym
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committedDec 4, 2021
updated screenshot to match rewired sch
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committedDec 4, 2021
cleaned up test bench wiring
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committedDec 4, 2021
sym for 2-tgates-2cap cell and test bench
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committedDec 4, 2021

Commits on Dec 3, 2021

sweeping characterization plots
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committedDec 3, 2021

Commits on Dec 2, 2021

dependent nonlinear source for ideal gaussian impulse response
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committedDec 2, 2021

Commits on Dec 1, 2021

cleaned up transmission gate sym, added tb to compare with only using nmos/pmos switches
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committedDec 1, 2021