This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

A small, light weight, RISC CPU soft core

Project demonstrating the design and testing of an 8 bit CPU in Verilog for EE4023 Digital IC Design module at UCC, 2020/2021

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

Visualizer for neural network, deep learning and machine learning models

A Walkie-Talkie based around the ESP32 using UDP broadcast or ESP-NOW

A voice-controlled robot using the ESP32 and TensorFlow Lite