Basic Simulink Blocks for modeling CDRs and PLLs

Matlab/Simulink code for studying CDR and equalization techinques

An implementation of the Multiple-Rotating-Clock-Phase Architecture for Clock and Data Recovery described by S. I. Ahmed and Tad A. Kwasniewski

Pseudo Random Number based Clock and Data Recovery circuits

Detailed Instructions on the creation of custom/modified DMA (attack) Firmware based on pcileech-fpga

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

pcileech-fpga with wireless card emulation

DMA-KillerWiFI-CFW-BYPASS

DMA firmware for fast builds

用fpga实现直流电机或永磁同步伺服电机的电流环控制

motor control SoC(arm, current control IP, Industrial Ethernet IP)

Hogge Phase EMFI Detector

Scala based HDL

Open source FPGA-based NIC and platform for in-network compute

HDL libraries and projects

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端…

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Verilog digital signal processing components

Open source FPGA-based NIC and platform for in-network compute

Verilog AXI components for FPGA implementation

This is an Ip design for AXI_Lite including master and slave in Vivado 2016.4

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Generic FIFO implementation with optional FWFT

openpilot is an operating system for robotics. Currently, it upgrades the driver assistance system in 275+ supported cars.