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fgpa

Here are 17 public repositories matching this topic...

dpretet / cdc

Repository gathering basic modules for CDC purpose

asic timing fifo cdc fgpa cross-domain-crossing pulse-synchronizer

Updated Dec 31, 2019
SystemVerilog

ZipCPU / dbgbus

A collection of debugging busses developed and presented at zipcpu.com

verilog debugging-tools wishbone fgpa verilator wishbone-bus

Updated Jan 18, 2024
Verilog

char-fish-after-lunch / SystemOnCat

An SoC with multiple RISC-V IMA processors.

riscv chisel3 fgpa

Updated Aug 1, 2018
Scala

atmughrabi / AccelGraph

Graph Processing Framework that supports || OpenMP || CAPI

Updated Jan 21, 2023
SystemVerilog

ASP-SoC / ASP-SoC.github.io

Audio Signal Processing SoC Project Website

audio university-project fpga-soc-linux de1-soc audio-signal-processing fpga-soc fgpa fpga-audio hardware-software-design

Updated Apr 6, 2017
HTML

iDoka / vivado.sublime-package

SublimeText (highlighting) plugin for working with Xilinx Vivado files (tcl, xdc, etc)

plugin syntax vhdl tcl rtl ip verilog xilinx vivado sublimetext sdc hdl fgpa xci xdc

Updated Oct 13, 2020

abaelen / FPGA-DEEDS-Training-Material

Covers the DEEDS training material for electronic Design

design vhdl electronic fgpa electronic-design-automation electronic-simulation

Updated Jan 23, 2021
VHDL

ErickOF / CE5303-Minimal-SoC-Design-for-Alarm-Clock

Minimal SoC design for alarm clock

c makefile assembly embedded-systems assembly-language alarm-clock systemverilog embedded-c fgpa assembly-x86

Updated Nov 12, 2020
C

mubaarik / 6.111_project

verilog fgpa fpga-programming digital-range-shooting-game

Updated Feb 9, 2017
Verilog

marplyn / Processor-Systems-Architecture

МИЭТ, курс "Архитектуры процессорных систем"

vhdl verilog fgpa

Updated Dec 26, 2022
Tcl

Harikesh16 / COL215_labs

It contains 10 assignments based on simulation and testing of hardware codes on BASYS board.

vhdl led-controller fgpa basys3-fpga

Updated Jun 15, 2022
VHDL

Haibo-S / Traffic-Light-Controller

Traffic Light Controller uses VHDL to control intersection traffic lights on an Altera MAX10 FPGA, simulating how to manage traffic signals and pedestrian requests.

Updated Apr 28, 2024
VHDL

paolopedroso / Dino-Run

This project implements a "Dino Run" game on a Basys 3 FPGA Board using SystemVerilog, with a state machine controlling game logic and VGA display output. The design includes modules for random number generation, obstacle management, and a score counter, all integrated to create a functional side-scrolling game.

state-machine verilog systemverilog fgpa sequential-circuit

Updated Aug 14, 2024
Verilog

tancredeguillou / Tetris

Tetris in low level programming. Made for Nios II processors.

fgpa nios-embedded-system

Updated Nov 8, 2021
Assembly

fernandolucasaa / Projet-Logique-Programmable

Updated Oct 17, 2019
VHDL

SemihAkkoc / EEE102

2022 Fall Bilkent EEE102

vhdl digital-design fgpa

Updated Mar 12, 2023

edcote / system99

systemverilog fgpa

Updated Sep 24, 2018
Verilog

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