CS8351 Digital Principles and System Design MCQ

CS8351 DPSD CSE - Regulations 2017
c) Adding
d) Subtracting
CS8351 DIGITAL
Answer: b
PRINCIPLES AND Explanation: On multiplying the decimal number
continuously by 2, the binary equivalent is obtained by
SYSTEM DESIGN the collection of the integer part. However, if it’s an
integer, then it’s binary equivalent is determined by
dividing the number by 2 and collecting the
CSE - 5th Semester remainders.
4. The representation of octal number (532.2)8 in

decimal is ________
a) (346.25)10
b) (532.864)10
UNIT I BOOLEAN ALGEBRA c) (340.67)10
d) (531.668)10
AND LOGIC GATES
Answer: a
Explanation: Octal to Decimal conversion is obtained
TOPIC 1.1 NUMBER SYSTEMS by multiplying 8 to the power of base index along with
the value at that index position.
1. Any signed negative binary number is recognised by (532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 =
its ________ (346.25)10
a) MSB
b) LSB 5. The decimal equivalent of the binary number
c) Byte (1011.011)2 is ________
d) Nibble a) (11.375)10
b) (10.123)10
Answer: a c) (11.175)10
Explanation: Any negative number is recognized by d) (9.23)10
its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive. Answer: a
Explanation: Binary to Decimal conversion is
2. The parameter through which 16 distinct values can obtained by multiplying 2 to the power of base index
be represented is known as ________ along with the value at that index position.
a) Bit 1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 *
b) Byte
c) Word 2-3 = (11.375)10
d) Nibble Hence, (1011.011)2 = (11.375)10
Answer: c 6. An important drawback of binary system is

Explanation: It can be represented up to 16 different ________
values with the help of a Word. Nibble is a a) It requires very large string of 1’s and 0’s to
combination of four bits and Byte is a combination of represent a decimal number
8 bits. It is “word” which is said to be a collection of b) It requires sparingly small string of 1’s and 0’s to
16-bits on most of the systems. represent a decimal number
c) It requires large string of 1’s and small string of 0’s
3. If the decimal number is a fraction then its binary to represent a decimal number
equivalent is obtained by ________ the number d) It requires small string of 1’s and large string of 0’s
continuously by 2. to represent a decimal number
a) Dividing
b) Multiplying Answer: a
Explanation: The most vital drawback of binary
system is that it requires very large string of 1’s and 0’s
Downloaded From: https://cse-r17.blogspot.com 1
to represent a decimal number. Hence, Hexadecimal c) 4 bits
systems are used by processors for calculation d) 8 bits
purposes as it compresses the long binary strings into
small parts. Answer: b
Explanation: One word means 16 bits, Thus, the
7. The decimal equivalent of the octal number (645)8 quantity of double word is 32 bits.
is ______
a) (450)10 TOPIC 1.2 ARITHMETIC OPERATIONS
b) (451)10
c) (421)10 This set of Digital Electronics/Circuits Multiple
d) (501)10 Choice Questions & Answers (MCQs) focuses on
“Arithmetic Operation”
Answer: c
Explanation: Octal to Decimal conversion is obtained 1. What is the addition of the binary numbers
by multiplying 8 to the power of base index along with 11011011010 and 010100101?
the value at that index position. a) 0111001000
The decimal equivalent of the octal number (645)8 is 6 b) 1100110110
c) 11101111111
* 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5 = 384 + 32 d) 10011010011
+ 5 = (421)10.
Answer: c
8. The largest two digit hexadecimal number is Explanation: The rules for Binary Addition are :
________ 0+0=0
a) (FE)16 0+1=1
b) (FD)16 1+0=1
c) (FF)16 1 + 1 = 0 ( Carry 1)
d) (EF)16
1
Answer: c
1 1 0 1 1 0 1 1 0 1 0
Explanation: (FE)16 is 254 in decimal system, while
(FD)16 is 253. (EF)16 is 239 in decimal system. And, + 0 0 0 1 0 1 0 0 1 0 1
(FF)16 is 255. Thus, The largest two-digit hexadecimal _______________________
number is (FF)16. 1 1 1 0 1 1 1 1 1 1 1
_______________________
9. Representation of hexadecimal number (6DE)H in
decimal: 2. Perform binary addition: 101101 + 011011 = ?
a) 011010
a) 6 * 162 + 13 * 161 + 14 * 160 b) 1010100
b) 6 * 162 + 12 * 161 + 13 * 160 c) 101110
c) 6 * 162 + 11 * 161 + 14 * 160 d) 1001000
d) 6 * 162 + 14 * 161 + 15 * 160
Answer: d
Answer: a Explanation:The rules for Binary Addition are :
Explanation: Hexadecimal to Decimal conversion is 0+0=0
obtained by multiplying 16 to the power of base index 0+1=1
along with the value at that index position. 1+0=1
In hexadecimal number D & E represents 13 & 14 1 + 1 = 0 ( Carry 1)
respectively. 1 1 1 1 1 1
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160. 1 0 1 1 0 1
+ 0 1 1 0 1 1
10. The quantity of double word is ________ _______________
1 0 0 1 0 0 0
a) 16 bits _______________
b) 32 bits

Therefore, the addition of 101101 + 011011 = 0*1=0
1001000. 1*0=0
1*1=1
3. Perform binary subtraction: 101111 – 010101 = ?
a) 100100 0 1 0 0 1
x 0 1 0 1 1
b) 010101 ____________
c) 011010 0 1 0 0 1
d) 011001 0 1 0 0 1 0
0 0 0 0 0 0 0
Answer: c 0 1 0 0 1 0 0 0
Explanation: The rules for Binary Subtraction are : 0 0 0 0 0 0 0 0 0
___________________
0–0=0 0 0 1 1 0 0 0 1 1
0 – 1 = 1 ( Borrow 1) ___________________
1–0=1
1–1=0 Therefore, 01001 × 01011 = 001100011.
1 0 1 1 1 1 6. 100101 × 0110 = ?
- 0 1 0 1 0 1
____________
a) 1011001111
0 1 1 0 1 0 b) 0100110011
_____________ c) 101111110
d) 0110100101
Therefore, The subtraction of 101111 – 010101 =
011010. Answer: c
Explanation: The rules for binary multiplication are:
4. Binary subtraction of 100101 – 011110 is 0*0=0
a) 000111 0*1=0
b) 111000 1*0=0
c) 010101 1*1=1
d) 101010
1 0 0 1 0 1
Answer: a x 0 1 1 0
___________
Explanation: The rules for Binary Subtraction are : 0 0 0 0 0 0
0–0=0 1 0 0 1 0 1 0
0 – 1 = 1 ( Borrow 1) 1 0 0 1 0 1 0 0
1–0=1 0 0 0 0 0 0 0 0 0
1–1=0 __________________
0 1 1 0 1 1 1 1 0
1 0 0 1 0 1 ___________________
- 0 1 1 1 1 0
___________ Therefore, 100101 x 0110 = 011011110.
0 0 0 1 1 1
___________ 7. On multiplication of (10.10) and (01.01), we get
a) 101.0010
Therefore, The subtraction of 100101 – 011110 = b) 0010.101
000111. c) 011.0010
d) 110.0011
5. Perform multiplication of the binary numbers:
01001 × 01011 = ? Answer: c
a) 001100011 Explanation: The rules for binary multiplication are:
b) 110011100 0*0=0
c) 010100110 0*1=0
d) 101010111 1*0=0
1*1=1
Answer: a
Explanation: The rules for binary multiplication are: 1 0.1 0
0*0=0 x 0 1.0 1

__________ 0 0 0 1 0 1
1 0 1 0 ________________________
0 0 0 0 0 1 0 1 0 1
1 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 0 ________________________
_______________ 1 0 0 0 0
0 1 1.0 0 1 0
_________________ Therefore, the quotient of 011010000 ÷ 1001 =
101001.
Therefore, 10.10 x 01.01 = 011.0010.
10. Binary subtraction of 101101 – 001011 = ?
8. Divide the binary numbers: 111101 ÷ 1001 and find a) 100010
the remainder b) 010110
a) 0010 c) 110101
b) 1010 d) 101100
c) 1100
d) 0011 Answer: a
Explanation: The rules for binary subtraction are:
Answer: d 0–0=0
Explanation: Binary Division is accomplished using 0 – 1 = 1 ( Borrow 1)
long division method. 1–0=1
1 0 0 1 ) 1 1 1 1 0 1 ( 1 1 1–1=0
1 0 0 1
__________ 1 0 1 1 0 1
0 1 1 0 0 - 0 0 1 0 1 1
1 0 0 1 ____________
___________ 1 0 0 0 1 0
0 1 1 1 ____________
Therefore, the remainder of 111101 ÷ 1001 = 0111. Therefore, the subtraction of 101101 – 001011 =
100010.
9. Divide the binary number (011010000) by (0101)
and find the quotient TOPIC 1.3 BINARY CODES
a) 100011
b) 101001
c) 110010 1. Binary coded decimal is a combination of
d) 010001 __________
a) Two binary digits
Answer: b b) Three binary digits
Explanation: c) Four binary digits
d) Five binary digits
0 1 0 1 ) 0 1 1 0 1 0 0 0 0 ( 0 1 0 1 1 1
0 0 0 0 Answer: c
_____________________ Explanation: Binary coded decimal is a combination
0 1 1 0 1
0 0 1 0 1 of 4 binary digits. For example-8421.
______________
0 1 0 0 0 0 2. The decimal number 10 is represented in its BCD
0 0 0 0 0 0 form as __________
______________________ a) 10100000
1 0 0 0 0
0 0 1 0 1
b) 01010111
____________________ c) 00010000
0 1 0 1 1 0 d) 00101011
0 0 0 1 0 1
____________________ Answer: c
1 0 0 0 1 0 Explanation: The decimal number 10 is represented in
0 0 0 1 0 1
________________________
its BCD form as 0001 0000, in accordance to 8421 for
1 1 1 0 1 0 each of the two digits.

3. Add the two BCD numbers: 1001 + 0100 = ? a) 3 bits
a) 10101111 b) 6 bits
b) 01010000 c) 12 bits
c) 00010011 d) 24 bits
d) 00101011
Answer: c
Answer: c Explanation: The number of bits needed to represent a
Explanation: Firstly, Add the 1001 and 0100. We get given decimal number is always greater than the
1101 as output but it’s not in BCD form. So, we add number of bits required for a straight binary encoding
0110 (i.e. 6) with 1101. As a result we get 10011 and of the same. Hence, a three digit decimal number
it’s BCD form is 0001 0011. requires 12 bits for representation in BCD format.
4. Carry out BCD subtraction for (68) – (61) using 8. How many bits would be required to encode
10’s complement method. decimal numbers 0 to 9999 in straight binary codes?
a) 00000111 a) 12
b) 01110000 b) 14
c) 100000111 c) 16
d) 011111000 d) 18
Answer: a Answer: b
Explanation: First the two numbers are converted into Explanation: Total number of decimals to be
their respective BCD form using 8421 sequence. Then represented = 10000 = 104 = 2n (where n is the number
binary subtraction is carried out.
of bits required) = 213.29. Therefore, the number of
bits required for straight binary encoding = 14.
5. Code is a symbolic representation of __________
information.
9. The excess-3 code for 597 is given by __________
a) Continuous
a) 100011001010
b) Discrete
b) 100010100111
c) Analog c) 010110010111
d) Both continuous and discrete
d) 010110101101
Answer: b Answer: a
Explanation: Code is a symbolic representation of
Explanation: The addition of ‘3’ to each digit yields
discrete information, which may be present in the form
the three new digits ‘8’, ’12’ and ’10’. Hence, the
of numbers, letters or physical quantities. Mostly, it is
corresponding four-bit binary equivalents are
represented using a particular number system like
100011001010, in accordance to 8421 format.
decimal or binary and such like.
10. The decimal equivalent of the excess-3 number
6. When numbers, letters or words are represented by a 110010100011.01110101 is _____________
special group of symbols, this process is called
a) 970.42
__________
b) 1253.75
a) Decoding
c) 861.75
b) Encoding
d) 1132.87
c) Digitizing
d) Inverting Answer: a
Explanation: The conversion of binary numbers into
Answer: b
digits ‘1100’, ‘1010’, ‘0011’, ‘0111’ and ‘0101’ gives
Explanation: When numbers, letters or words are
’12’, ‘5’, ‘3’, ‘7’ and ‘5’ respectively. Hence, the
represented by a special group of symbols, this process
decimal number is 970.42.
is called encoding. Encoding in the sense of fetching
the codes or words in a computer. It is done to secure
the transmission of information. TOPIC 1.4 BOOLEAN ALGEBRA AND
LOGIC GATES
7. A three digit decimal number requires ________ for
representation in the conventional BCD format.

1. In boolean algebra, the OR operation is performed Answer: d
by which properties? Explanation: A(A + B) = AA + AB (By Distributive
a) Associative properties Property) = A + AB (A.A = A By Commutative
b) Commutative properties Property) = A(1 + B) = A*1 (1 + B = 1 by 1’s
c) Distributive properties Property) = A.
d) All of the Mentioned
6. DeMorgan’s theorem states that _________
Answer: d a) (AB)’ = A’ + B’
Explanation: The expression for Associative property b) (A + B)’ = A’ * B
is given by A+(B+C) = (A+B)+C & A*(B*C) = c) A’ + B’ = A’B’
(A*B)*C. d) (AB)’ = A’ + B
The expression for Commutative property is given by
A+B = B+A & A*B = B*A. Answer: a
The expression for Distributive property is given by Explanation: The DeMorgan’s law states that (AB)’ =
A+BC=(A+B)(A+C) & A(B+C) = AB+AC. A’ + B’ & (A + B)’ = A’ * B’, as per the Dual
Property.
2. The expression for Absorption law is given by
_________ 7. (A + B)(A’ * B’) = ?
a) A + AB = A a) 1
b) A + AB = B b) 0
c) AB + AA’ = A c) AB
d) A + B = B + A d) AB’
Answer: a Answer: b
Explanation: The expression for Absorption Law is Explanation: The DeMorgan’s law states that (AB)’ =
given by: A+AB = A. A’ + B’ & (A + B)’ = A’ * B’, as per the Dual
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per Property.
1’s Property).
8. Complement of the expression A’B + CD’ is
3. According to boolean law: A + 1 = ? _________
a) 1 a) (A’ + B)(C’ + D)
b) A b) (A + B’)(C’ + D)
c) 0 c) (A’ + B)(C’ + D)
d) A’ d) (A + B’)(C + D’)
Answer: a Answer: b
Explanation: A + 1 = 1, as per 1’s Property. Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By
DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By
4. The involution of A is equal to _________ DeMorgan’s Theorem) = (A + B’)(C’ + D).
a) A
b) A’ 9. Simplify Y = AB’ + (A’ + B)C.
c) 1 a) AB’ + C
d) 0 b) AB + AC
c) A’B + AC’
Answer: a d) AB + A
Explanation: The involution of A means double
inversion of A (i.e. A”) and is equal to A. Answer: a
Proof: ((A)’)’ = A Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C
= (AB’ + C)( AB’ + AB’) = (AB’ + C).1 = (AB’ + C).
5. A(A + B) = ?
a) AB 10. The boolean function A + BC is a reduced form of
b) 1 ____________
c) (1 + AB) a) AB + BC
d) A b) (A + B)(A + C)

c) A’B + AB’C a) One
d) (A + C)B b) Two
c) Three
Answer: b d) Four
Explanation: (A + B)(A + C) = AA + AC + AB + BC
= A + AC + AB + BC (By Commutative Property) = Answer: c
A(1 + C + B) + BC = A + BC (1 + B + C =1 By 1’s Explanation: Y = A + B. This is the equation of OR
Property). gate. We require 3 NAND gates to create OR gate. We
can also write,
1st, 2nd and 3rd NAND operations as: Y = ((NOT A)
TOPIC 1.5 THEOREMS AND AND (NOT B))’ = A’’ + B’’ = (A+B).
PROPERTIES OF BOOLEAN
ALGEBRA 5. Odd parity of word can be conveniently tested by
___________
1. The output of an EX-NOR gate is 1. Which input a) OR gate
combination is correct? b) AND gate
a) A = 1, B = 0 c) NAND gate
b) A = 0, B = 1 d) XOR gate
c) A = 0, B = 0
Answer: d
d) A = 0, B’ = 1
Explanation: Odd parity of word can be conveniently
Answer: c tested by XOR gate, since, XOR outputs 1 only when
Explanation: The output of EX-NOR gate is given by the input has odd number of 1’s.
AB + A’B’. So, for A = 0 and B = 0 the output will be
6. The number of full and half adders are required to
1.
add 16-bit number is __________
2. In which of the following gates the output is 1 if and a) 8 half adders, 8 full adders
only if at least one input is 1? b) 1 half adders, 15 full adders
a) AND c) 16 half adders, 0 full adders
b) NOR d) 4 half adders, 12 full adders
c) NAND
Answer: b
d) OR
Explanation: Half adder has two inputs and two
Answer: d outputs whereas Full Adder has 3 inputs and 2 outputs.
Explanation: In or gate we need at least one bit to be One half adder can add the least significant bit of the
equal to 1 to generate the output as 1 because OR two numbers whereas full adders are required to add
means any of the condition out of two is equal to 1 the remaining 15 bits as they all involve adding
which means if at least one input is 1 then it shows carries.
output as 1.
7. Which of the following will give the sum of full
3. The time required for a gate or inverter to change its adders as output?
state is called __________ a) Three point major circuit
a) Rise time b) Three bit parity checker
b) Decay time c) Three bit comparator
c) Propagation time d) Three bit counter
d) Charging time
Answer: d
Answer: c Explanation: Counters are used for counting purposes
Explanation: The time required for a gate or inverter in ascending or descending order. Three bit counter
to change its state is called propagation time. will give the sum of full adders as output.
4. What is the minimum number of two input NAND 8. Which of the following gate is known as
gates used to perform the function of two input OR coincidence detector?
gates? a) AND gate
b) OR gate

c) NOR gate Answer: a
d) NAND gate Explanation: This is a boolean expression. It can be
evaluated as :
Answer: a X+X.Y = X(1+Y) = X.
Explanation: AND gate is known as coincidence Since 1+Y=1 by boolean laws.
detector due to multiplicity behaviour, as it outputs 1
only when all the inputs are 1. 3. In the boolean function w=f(X,Y,Z), what is the
RHS referred to as ________
9. An OR gate can be imagined as ____________ a) right hand side
a) Switches connected in series b) expression
b) Switches connected in parallel c) literals
c) MOS transistor connected in series d) boolean
d) BJT transistor connected in series
Answer: b
Answer: b Explanation: The RHS is commonly referred to as the
Explanation: OR gate means addition of two inputs, expression. The symbols X, Y and Z are commonly
which outputs when any of the input is high. Due to referred to as the literals of the function.
this reason, it is imagined as switches connected in
parallel. 4. The general form for calculating the number of rows
in a truth table is ________
10. How many full adders are required to construct an a) 2n
m-bit parallel adder?
b) 2n+1
a) m/2
b) m c) 2n
c) m-1 d) 2n+1
d) m+1
Answer: c
Answer: c Explanation: The general form for the calculation of
Explanation: We need adder for every bit. So we rows in a truth table is 2n . Here, n= number of literals
should need m bit adders. A full adder adds a carry bit in the function.
to two inputs and produces an output and a carry. But
the most significant bits can use a half adder which 5. The number of literals in the expression F=X.Y’ + Z
differs from the full adder as in that it has no carry are _____________
input, so we need m-1 full adders and 1 half adder in a) 4
m bit parallel adder. b) 3
c) 2
TOPIC 1.6 BOOLEAN FUNCTIONS d) 1
Answer: b
1. Boolean Function is of the form of ________ Explanation: Literals the generally the number of
a) Truth values variables used in any boolean expression. Here, since
b) K=f(X,Y,X) there are 3 variables X, Y and Z, therefore the answer
c) Algebraic Expression is 3.
d) Truth Table
6. The complement term for X’.Y’.Z + X.Y will be
Answer: a _____________
Explanation: The boolean function is of the form of a) XYZ’+X’Y’
algebraic expressions or truth table. A boolean b) (X+Y+Z’)(X’+Y’)
function is of the form as that of option 2. The result c) (X+Y+Z’)(X’+Y)
obtained from a boolean function can be a truth value d) (X+Y+Z’)(X’+Y)
or a fallacy.
Answer: b
2. The result of X+X.Y is X. Explanation: The OR and AND operators are
a) True interchanged. The complement terms are reduced to
b) False normal terms and the result is obtained.
7. What is the complement of X’Y’Z? c) OR operation
a) X+YZ d) NAND operation
b) X’+Y+’Z’
c) X+Y+Z’ Answer: a
d) XYZ’ Explanation: The logical sum of two or more logical
product terms, is called SOP (i.e. sum of product). The
Answer: c logical product of two or more logical sum terms, is
Explanation: The complement is obtained by called POS (i.e. product of sums).
converting the complement terms to normal terms and
vice versa. Also, the OR and AND operators are 2. The expression Y=AB+BC+AC shows the
interchanged. Here, X’Y’Z gets converted to X+Y+Z’. _________ operation.
a) EX-OR
8. The minterm of any expression is denoted by b) SOP
___________ c) POS
a) Mt d) NOR
b) m
c) M Answer: b
d) min Explanation: The given expression has the operation
product as well as the sum of that. So, it shows SOP
Answer: b operation. POS will be the product of sum terms.
Explanation: The variables forming an AND term is
generally the minterm. It is denoted by m. (lower case 3. The expression Y=(A+B)(B+C)(C+A) shows the
letter). _________ operation.
a) AND
9. The min term when X=Y=Z=0 is _____________ b) POS
a) x’+y’+z’ c) SOP
b) xyz d) NAND
c) x’y’z’
d) x+y+z Answer: b
Explanation: The given expression has the operation
Answer: c sum as well as the product of that. So, it shows
Explanation: There minterm expression is obtained POS(product of sum) operation. SOP will be the sum
using the AND term. Here, when X=Y=Z=0, the of product terms.
expression obtained is x’y’z’.
4. A product term containing all K variables of the
10. The max term when X=Y=Z=1 is ________ function in either complemented or uncomplemented
a) x’+y’+z’ form is called a __________
b) xyz a) Minterm
c) x’y’z’ b) Maxterm
d) x+y+z c) Midterm
d) ∑ term
Answer: a
Explanation: The max term consists of variables Answer: a
forming an OR term. Here, when X=Y=Z=1, the Explanation: A product term containing all K
expression is x’+y’+z’. variables of the function in either complemented or
uncomplemented form is called a minterm. A sum
term containing all K variables of the function in either
TOPIC 1.7 CANONICAL AND complemented or uncomplemented form is called a
STANDARD FORMS maxterm.
1. The logical sum of two or more logical product 5. According to the property of minterm, how many
terms is called __________ combination will have value equal to 1 for K input
a) SOP variables?
b) POS a) 0
b) 1

c) 2 10. There are _____________ Minterms for 3
d) 3 variables (a, b, c).
a) 0
Answer: b b) 2
Explanation: The main property of a minterm is that it c) 8
possesses the value 1 for only one combination of K d) 1
input variables and the remaining will have the value
0. Answer: c
Explanation: Minterm is given by 2n. So, 23 = 8
6. The canonical sum of product form of the function minterms are required.
y(A,B) = A + B is __________
a) AB + BB + A’A 11. _____________ expressions can be implemented
b) AB + AB’ + A’B using either (1) 2-level AND-OR logic circuits or (2)
c) BA + BA’ + A’B’ 2-level NAND logic circuits.
d) AB’ + A’B + A’B’ a) POS
b) Literals
Answer: b c) SOP
Explanation: A + B = A.1 + B.1 = A(B + B’) + B(A + d) POS
A’) = AB + AB’ + BA +BA’ = AB + AB’ + A’B = AB
+ AB’ + A’B. Answer: c
Explanation: SOP expressions can be implemented
7. A variable on its own or in its complemented form using either (1) 2-level AND-OR logic circuits or (2)
is known as a __________ 2-level NAND logic circuits.
a) Product Term
b) Literal
c) Sum Term TOPIC 1.8 SIMPLIFICATION OF
d) Word BOOLEAN FUNCTIONS USING
KARNAUGH MAP
Answer: b
Explanation: A literal is a single logic variable or its
complement. For example — X, Y, A’, Z, X’ etc. 1. A Karnaugh map (K-map) is an abstract form of
____________ diagram organized as a matrix of
8. Maxterm is the sum of __________ of the squares.
corresponding Minterm with its literal complemented. a) Venn Diagram
a) Terms b) Cycle Diagram
b) Words c) Block diagram
c) Numbers d) Triangular Diagram
d) Nibble
Answer: a
Answer: a Explanation: A Karnaugh map (K-map) is an abstract
Explanation: Maxterm is the sum of terms of the form of Venn diagram organized as a matrix of
corresponding Minterm with its literal complemented. squares, where each square represents a Maxterm or a
Minterm.
9. Canonical form is a unique way of representing
____________ 2. There are ______ cells in a 4-variable K-map.
a) SOP a) 12
b) Minterm b) 16
c) Boolean Expressions c) 18
d) POS d) 8
Answer: c Answer: b
Explanation: Boolean Expressions are represented Explanation: There are 16 = (24) cells in a 4-variable
through canonical form. An example of canonical form K-map.
is A’B’C’ + AB’C + ABC’.

3. The K-map based Boolean reduction is based on the c) Set
following Unifying Theorem: A + A’ = 1. d) Word
a) Impact
b) Non Impact Answer: a
c) Force Explanation: Each group of adjacent Minterms (group
d) Complementarity size in powers of twos) corresponds to a possible
product term of the given function.
Answer: b
Explanation: The given expression A +A’ = 1 is based 8. Don’t care conditions can be used for simplifying
on non-impact unifying theorem. Boolean expressions in ___________
a) Registers
4. Each product term of a group, w’.x.y’ and w.y, b) Terms
represents the ____________in that group. c) K-maps
a) Input d) Latches
b) POS
c) Sum-of-Minterms Answer: c
d) Sum of Maxterms Explanation: Don’t care conditions can be used for
simplifying Boolean expressions in K-maps which
Answer: c helps in pairing with 1/0.
Explanation: In a minterm, each variable w, x or y
appears once either as the variable itself or as the 9. It should be kept in mind that don’t care terms
inverse. So, the given expression satisfies the property should be used along with the terms that are present in
of Sum of Minterm. ___________
a) Minterms
5. The prime implicant which has at least one element b) Expressions
that is not present in any other implicant is known as c) K-Map
___________ d) Latches
a) Essential Prime Implicant
b) Implicant Answer: a
c) Complement Explanation: It should be kept in mind that don’t care
d) Prime Complement terms should be used along with the terms that are
present in minterms as well as maxterms which
Answer: a reduces the complexity of the boolean expression.
Explanation: Essential prime implicants are prime
implicants that cover an output of the function that no 10. Using the transformation method you can realize
combination of other prime implicants is able to cover. any POS realization of OR-AND with only.
a) XOR
6. Product-of-Sums expressions can be implemented b) NAND
using ___________ c) AND
a) 2-level OR-AND logic circuits d) NOR
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits Answer: d
d) Both 2-level OR-AND and NOR logic circuits Explanation: Using the transformation method we can
realize any POS realization of OR-AND with only
Answer: d NOR.
Explanation: Product-of-Sums expressions can be
implemented using 2-level OR-AND & NOR logic 11. There are many situations in logic design in which
circuits. simplification of logic expression is possible in terms
of XOR and _________________ operations.
7. Each group of adjacent Minterms (group size in a) X-NOR
powers of twos) corresponds to a possible product b) XOR
term of the given ___________ c) NOR
a) Function d) NAND
b) Value

Answer: a A B C
Explanation: There are many situations in logic 0 0 1
design in which simplification of logic expression is
0 1 0
possible in terms of XOR and XNOR operations.
Expression of XOR : AB’ + A’B 1 0 0
Expression of XNOR : AB + A’B’ 1 1 0
INPUT OUTPUT
12. These logic gates are widely used in
_______________ design and therefore are available A B C
in IC form. 0 0 1
a) Sampling 0 1 0
b) Digital 1 0 0
c) Analog
1 1 1
d) Systems
Answer: b The gate is either _________

Explanation: These logic gates(XOR,XNOR,NOR) a) A NAND or an EX-OR
are widely used in digital design and therefore are b) An OR or an EX-NOR
available in IC form as digital circuits deals with data c) An AND or an EX-OR
transmission in the form of binary digits. d) A NOR or an EX-NOR
13. In case of XOR/XNOR simplification we have to Answer: d

look for the following _______________ Explanation: The output of a logic gate is 1 when all
a) Diagonal Adjacencies inputs are at logic 0. The gate is NOR. The output of a
b) Offset Adjacencies logic gate is 1 when all inputs are at logic 0 or all
c) Straight Adjacencies inputs are at logic 1, then it is EX-NOR. (The truth
d) Both diagonal and offset adjencies tables for NOR and EX-NOR Gates are shown in
above table).
Answer: d
Explanation: In case of XOR/XNOR simplification 2. The code where all successive numbers differ from
we have to look for the following diagonal and offset their preceding number by single bit is __________
adjacencies. XOR gives output 1 when odd number of a) Alphanumeric Code
1s are present in input while XNOR gives output 1 b) BCD
when even number of 1s or all 0s are present in input. c) Excess 3
d) Gray
14. Entries known as _______________ mapping.
a) Diagonal Answer: d
b) Straight Explanation: The code where all successive numbers
c) K differ from their preceding number by single bit is gray
d) Boolean code. It is an unweighted code. The most important
characteristic of this code is that only a single bit
Answer: a change occurs when going from one code number to
Explanation: Entries known as diagonal mapping. The next. BCD Code is one in which decimal digits are
diagonal mapping holds true when for any relation, represented by a group of 4-bits each, whereas, in
there is a projection of product on the factor. Excess-3 Code, the decimal numbers are incremented
by 3 and then written in their BCD format.
TOPIC 1.9 LOGIC GATES, NAND AND 3. The following switching functions are to be
NOR IMPLEMENTATIONS implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 =
∑m(2, 4, 5, 6, 7)
1. The output of a logic gate is 1 when all the input are
The minimum configuration of decoder will be
at logic 0 as shown below:
__________
a) 2 to 4 line
INPUT OUTPUT
b) 3 to 8 line

c) 4 to 16 line 8. A full adder logic circuit will have __________
d) 5 to 32 line a) Two inputs and one output
b) Three inputs and three outputs
Answer: c c) Two inputs and two outputs
Explanation: 4 to 16 line decoder as the minterms are d) Three inputs and two outputs
ranging from 1 to 14.
Answer: d
4. How many AND gates are required to realize Y = Explanation: A full adder circuit will add two bits and
CD + EF + G? it will also accounts the carry input generated in the
a) 4 previous stage. Thus three inputs and two outputs
b) 5 (Sum and Carry) are there. In case of half adder
c) 3 circuit, there are only two inputs bits and two outputs
d) 2 (SUM and CARRY).
Answer: d 9. How many two input AND gates and two input OR
Explanation: To realize Y = CD + EF + G, two AND gates are required to realize Y = BD + CE + AB?
gates are required and two OR gates are required. a) 3, 2
b) 4, 2
5. The NOR gate output will be high if the two inputs c) 1, 1
are __________ d) 2, 3
a) 00
b) 01 Answer: a
c) 10 Explanation: There are three product terms. So, three
d) 11 AND gates of two inputs are required. As only two
input OR gates are available, so two OR gates are
Answer: a required to get the logical sum of three product terms.
Explanation: In 01, 10 or 11 output is low if any of
the I/P is high. So, the correct option will be 00. 10. Which of following are known as universal gates?
a) NAND & NOR
6. How many two-input AND and OR gates are b) AND & OR
required to realize Y = CD+EF+G? c) XOR & OR
a) 2, 2 d) EX-NOR & XOR
b) 2, 3
c) 3, 3 Answer: a
d) 3, 2 Explanation: The NAND & NOR gates are known as
universal gates because any digital circuit can be
Answer: a realized completely by using either of these two gates,
Explanation: Y = CD + EF + G and also they can generate the 3 basic gates AND, OR
The number of two input AND gate = 2 and NOT.
The number of two input OR gate = 2.
11. The gates required to build a half adder are
7. A universal logic gate is one which can be used to __________
generate any logic function. Which of the following is a) EX-OR gate and NOR gate
a universal logic gate? b) EX-OR gate and OR gate
a) OR c) EX-OR gate and AND gate
b) AND d) EX-NOR gate and AND gate
c) XOR
d) NAND Answer: c
Explanation: The gates required to build a half adder
Answer: d are EX-OR gate and AND gate. EX-OR outputs the
Explanation: An Universal Logic Gate is one which SUM of the two input bits whereas AND outputs the
can generate any logic function and also the three CARRY of the two input bits.
basic gates: AND, OR and NOT. Thus, NOR and
NAND can generate any logic function and are thus
Universal Logic Gates.

UNIT II COMBINATIONAL 2. Which of the following logic expressions represents

the logic diagram shown?
LOGIC
TOPIC 2.1 COMBINATIONAL
CIRCUITS
1. Which of the circuits in figure (a to d) is the sum-of-

products implementation of figure (e)?
a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
Answer: d
Explanation: 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.
3. The device shown here is most likely a ________
a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
Answer: d
Explanation: The given diagram is demultiplexer,
because it takes single input & gives many outputs. A
demultiplexer is a combinational circuit that takes a
single output and latches it to multiple outputs
depending on the select lines.
4. What type of logic circuit is represented by the

a) a figure shown below?
b) b
c) c
d) d
Answer: d
Explanation: SOP means Sum Of Products form
which represents the sum of product terms having
variables in complemented as well as in
uncomplemented form. Here, the diagram of d
contains the OR gate followed by the AND gates, so it a) XOR
is in SOP form. b) XNOR

c) AND input NAND gate, one inverter option only. A decoder
d) XAND is a combinational circuit that converts binary data to
n-coded data upto 2n outputs.
Answer: b
Explanation: After solving the circuit we get 7. What is the indication of a short to ground in the
(A’B’)+AB as output, which is XNOR operation. output of a driving gate?
Thus, it will produce 1 when inputs are even number a) Only the output of the defective gate is affected
of 1s or all 0s, and produce 0 when input is odd b) There is a signal loss to all load gates
number of 1s. c) The node may be stuck in either the HIGH or the
LOW state
5. For a two-input XNOR gate, with the input d) The affected node will be stuck in the HIGH state
waveforms as shown below, which output waveform is
correct? Answer: b
Explanation: Short to ground in the output of a
driving gate indicates of a signal loss to all load gates.
This results in information being disrupted and loss of
data.
8. For the device shown here, assume the D input is

LOW, both S inputs are LOW and the input is LOW.
What is the status of the Y’ outputs?
a) d
b) a a) All are HIGH
c) c b) All are LOW
d) b c) All but Y0 are LOW
d) All but Y0 are HIGH
Answer: a
Explanation: When both inputs are same then the o/p Answer: d
is high for a XNOR gate. Explanation: In the given diagram, S0 and S1 are
i.e., A B O/P selection bits. So,
001 I/P S0 S1 O/P
010 D = 0 0 0 Y0
100 D = 0 0 1 Y1
1 1 1. D = 0 1 0 Y2
Thus, it will produce 1 when inputs are even number D = 0 1 1 Y3
of 1s or all 0s, and produce 0 when input is odd Hence, inputs are S0 and S1 are Low means 0, so
number of 1s. output is Y0 and rest all are HIGH.
6. Which of the following combinations of logic gates 9. The carry propagation can be expressed as
can decode binary 1101? ________
a) One 4-input AND gate a) Cp = AB
b) One 4-input AND gate, one inverter b) Cp = A + B
c) One 4-input AND gate, one OR gate c) All but Y0 are LOW
d) One 4-input NAND gate, one inverter d) All but Y0 are HIGH
Answer: b Answer: b
Explanation: For decoding any number output must Explanation: This happens in parallel adders (where
be high for that code and this is possible in One 4- we try to add numbers in parallel via more than one

adders). A carry propagation occurs when carry from b) Intermediate values
one adder needs to be forwarded to other adder and c) Input values
that second adder is holding the computation d) Clock pulses
(addition) because carry from first adder has not come
yet. So, there is a slight delay for second adder and this Answer: c
is known as carry propagation. Explanation: In a combinational circuit, the output at
any time depends only on the input values at that time
10. 3 bits full adder contains ________ and not on past or intermediate values.
a) 3 combinational inputs
b) 4 combinational inputs 4. In a sequential circuit, the output at any time
c) 6 combinational inputs depends only on the input values at that time.
d) 8 combinational inputs a) Past output values
b) Intermediate values
Answer: d c) Both past output and present input
Explanation: Full Adder is a combinational circuit d) Present input values
with 3 input bits and 2 output bits CARRY and SUM.
Three bits full adder requires 23 = 8 combinational Answer: c
circuits. Explanation: In a sequential circuit, the output at any
time depends on the present input values as well as
past output values. It also depends on clock pulses
TOPIC 2.2 ANALYSIS AND DESIGN depending whether it’s synchronous or asynchronous
PROCEDURES sequential circuits.
5. Procedure for the design of combinational circuits

1. The basic building blocks of the arithmetic unit in a
are:
digital computers are ____________
A. From the word description of the problem, identify
a) Subtractors
the inputs and outputs and draw a block diagram.
b) Adders
B. Draw the truth table such that it completely
c) Multiplexer
describes the operation of the circuit for different
d) Comparator
combinations of inputs.
Answer: b C. Simplify the switching expression(s) for the
Explanation: The basic building blocks of the output(s).
arithmetic unit in a digital computers are adders. Since, D. Implement the simplified expression using logic
a parallel adder is constructed with a number of full- gates.
adder circuits connected in cascade. By controlling the E. Write down the switching expression(s) for the
data inputs to the parallel adder, it is possible to obtain output(s).
different types of arithmetic operations. a) B, C, D, E, A
b) A, D, E, B, C
2. A digital system consists of _____ types of circuits. c) A, B, E, C, D
a) 2 d) B, A, E, C, D
b) 3
c) 4 Answer: c
d) 5 Explanation: Combinational circuits are the ones
which do not depend on previous inputs and depends
Answer: a only on the present values. The given arrangement in
Explanation: A digital system consists of two types of option c is the right sequence for the designing of the
circuits and these are combinational and sequential combinational circuits.
logic circuit. Combinational circuits are the ones
which do not depend on previous inputs while 6. All logic operations can be obtained by means of
Sequential circuits depend on past inputs. ____________
a) AND and NAND operations
3. In a combinational circuit, the output at any time b) OR and NOR operations
depends only on the _______ at that time. c) OR and NOT operations
a) Voltage d) NAND and NOR operations

Answer: d sometimes called condition code bits or flag bits. It is
Explanation: Since, the logic gates NOR and NAND so called because they tend to represent the status of
are known as universal logic gates, therefore it can be the respect flags after any operation.
used to design all the three basic gates AND, OR and
NOT. Thus, it means that any operations can be
obtained by implementation of these gates.
TOPIC 2.3 BINARY ADDER
7. The design of an ALU is based on ____________ 1. In parts of the processor, adders are used to calculate
a) Sequential logic ____________
b) Combinational logic a) Addresses
c) Multiplexing b) Table indices
d) De-Multiplexing c) Increment and decrement operators
Answer: b
Explanation: The design of an ALU is based on Answer: d
combinational logic. Because the unit has a regular Explanation: Adders are used to perform the
pattern, it can be broken into identical stages operation of addition. Thus, in parts of the processor,
connected in cascade through carries. adders are used to calculate addresses, table indices,
increment and decrement operators, and similar
8. If the two numbers are unsigned, the bit conditions operations.
of interest are the ______ carry and a possible _____
result. 2. Total number of inputs in a half adder is
a) Input, zero __________
b) Output, one a) 2
c) Input, one b) 3
d) Output, zero c) 4
d) 1
Answer: d
Explanation: If the two numbers are unsigned, the bit Answer: a
conditions of interest are the output carry and a Explanation: Total number of inputs in a half adder is
possible zero result. two. Since, an EXOR gates has 2 inputs and carry is
connected with the input of EXOR gates. The output
9. If the two numbers include a sign bit in the highest of half-adder is also 2, them being, SUM and CARRY.
order position, the bit conditions of interest are the The output of EXOR gives SUM and that of AND
sign of the result, a zero indication and ___________ gives carry.
a) An underflow condition
b) A neutral condition 3. In which operation carry is obtained?
c) An overflow condition a) Subtraction
d) One indication b) Addition
c) Multiplication
Answer: c d) Both addition and subtraction
Explanation: If the two numbers include a sign bit in
the highest order position, the bit conditions of interest Answer: b
are the sign of the result, a zero indication and an Explanation: In addition, carry is obtained. For
overflow condition. example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is
obtained after 1st addition (i.e. 1 + 1 = 1 0). In
10. The flag bits in an ALU is defined as subtraction, borrow is obtained. Like, 0 – 1 = 1
____________ (borrow 1).
a) The total number of registers
b) The status bit conditions 4. If A and B are the inputs of a half adder, the sum is
c) The total number of control lines given by __________
d) All of the Mentioned a) A AND B
b) A OR B
Answer: b c) A XOR B
Explanation: In an ALU, status bit conditions are d) A EX-NOR B
Answer: c Answer: c
Explanation: If A and B are the inputs of a half adder, Explanation: If A, B and C are the inputs of a full
the sum is given by A XOR B, while the carry is given adder then the sum is given by A XOR B XOR C.
by A AND B.
9. If A, B and C are the inputs of a full adder then the
5. If A and B are the inputs of a half adder, the carry is carry is given by __________
given by __________ a) A AND B OR (A OR B) AND C
a) A AND B b) A OR B OR (A AND B) C
b) A OR B c) (A AND B) OR (A AND B)C
c) A XOR B d) A XOR B XOR (A XOR B) AND C
d) A EX-NOR B
Answer: a
Answer: a Explanation: If A, B and C are the inputs of a full
Explanation: If A and B are the inputs of a half adder, adder then the carry is given by A AND B OR (A OR
the carry is given by: A(AND)B, while the sum is B) AND C, which is equivalent to (A AND B) OR (B
given by A XOR B. AND C) OR (C AND A).
6. Half-adders have a major limitation in that they 10. How many AND, OR and EXOR gates are
cannot __________ required for the configuration of full adder?
a) Accept a carry bit from a present stage a) 1, 2, 2
b) Accept a carry bit from a next stage b) 2, 1, 2
c) Accept a carry bit from a previous stage c) 3, 1, 2
d) Accept a carry bit from the following stages d) 4, 0, 1
Answer: c Answer: b
Explanation: Half-adders have a major limitation in Explanation: There are 2 AND, 1 OR and 2 EXOR
that they cannot accept a carry bit from a previous gates required for the configuration of full adder,
stage, meaning that they cannot be chained together to provided using half adder. Otherwise, configuration of
add multi-bit numbers. However, the two output bits of full adder would require 3 AND, 2 OR and 2 EXOR.
a half-adder can also represent the result A+B=3 as
sum and carry both being high.
TOPIC 2.4 BINARY SUBTRACTOR
7. The difference between half adder and full adder is
__________ 1. Half subtractor is used to perform subtraction of
a) Half adder has two inputs while full adder has four ___________
inputs a) 2 bits
b) Half adder has one output while full adder has two b) 3 bits
outputs c) 4 bits
c) Half adder has two inputs while full adder has three d) 5 bits
inputs
d) All of the Mentioned Answer: a
Explanation: Half subtractor is a combinational circuit
Answer: c which is used to perform subtraction of two bits,
Explanation: Half adder has two inputs while full namely minuend and subtrahend and produces two
adder has three outputs; this is the difference between outputs, borrow and difference.
them, while both have two outputs SUM and CARRY.
2. For subtracting 1 from 0, we use to take a _______
8. If A, B and C are the inputs of a full adder then the from neighbouring bits.
sum is given by __________ a) Carry
a) A AND B AND C b) Borrow
b) A OR B AND C c) Input
c) A XOR B XOR C d) Output
d) A OR B OR C
Answer: b
Explanation: For subtracting 1 from 0, we use to take

a borrow from neighbouring bits because carry is taken a) Their corresponding bits of input
into consideration during addition process. b) Its outputs
c) Its inputs
3. How many outputs are required for the d) Borrow bits
implementation of a subtractor?
a) 1 Answer: c
b) 2 Explanation: Minuend and subtrahend are the two bits
c) 3 of input of a subtractor. If A and B are the two inputs
d) 4 of a subtractor then A is called minuend and B as
subtrahend.
Answer: b
Explanation: There are two outputs required for the 8. Full subtractor is used to perform subtraction of
implementation of a subtractor. One for the difference ___________
and another for borrow. a) 2 bits
b) 3 bits
4. Let the input of a subtractor is A and B then what c) 4 bits
the output will be if A = B? d) 8 bits
a) 0
b) 1 Answer: b
c) A Explanation: Full subtractor is used to perform
d) B subtraction of 3 bits, namely minuend bit, subtrahend
bit and borrow from the previous stage. However, it
Answer: a also produces 2 outputs BORROW and
Explanation: The output for A = B will be 0. If A = B, DIFFERENCE.
it means that A = B = 0 or A = B = 1. In both of the
situation subtractor gives 0 as the output. 9. The full subtractor can be implemented using
___________
5. Let A and B is the input of a subtractor then the a) Two XOR and an OR gates
output will be ___________ b) Two half subtractors and an OR gate
a) A XOR B c) Two multiplexers and an AND gate
b) A AND B d) Two comparators and an AND gate
c) A OR B
d) A EXNOR B Answer: b
Explanation: A full subtractor has 3 input bits and two
Answer: a outputs bits BORROW and DIFFERENCE. The full
Explanation: The subtractor has two outputs BOROW subtractor can be implemented using two half
and DIFFERENCE. Since, the difference output of a subtractors and an OR gate.
subtractor is given by AB’ + BA’ and this is the output
of a XOR gate. So, the final difference output is AB’ + 10. The output of a subtractor is given by (if A, B and
BA’. X are the inputs).
a) A AND B XOR X
6. Let A and B is the input of a subtractor then the b) A XOR B XOR X
borrow will be ___________ c) A OR B NOR X
a) A AND B’ d) A NOR B XOR X
b) A’ AND B
c) A OR B Answer: b
d) A AND B Explanation: The difference output of a subtractor is
given by (if A, B and X are the inputs) A XOR B XOR
Answer: b X.
Explanation: The borrow of a subtractor is received
through AND gate whose one input is inverted. On 11. The output of a full subtractor is same as
that basis the borrow will be (A’ AND B). ____________
a) Half adder
7. What does minuend and subtrahend denotes in a b) Full adder
subtractor?

c) Half subtractor 4. The output sum of two decimal digits can be
d) Decoder represented in ____________
a) Gray Code
Answer: b b) Excess-3
Explanation: The sum and difference output of a full c) BCD
adder and a full subtractor are same. If A, B and C are d) Hexadecimal
the input of a full adder and a full subtractor then the
output will be given by (A XOR B XOR C), Answer: c
respectively. Explanation: The output sum of two decimal digits
can be represented in BCD(Binary-coded decimal).
Binary-coded decimal (BCD) is a class of binary
TOPIC 2.5 DECIMAL ADDER encodings of decimal numbers where each decimal
digit is represented by a fixed number of bits, usually
1. The decimal number system represents the decimal four or eight.
number in the form of ____________
a) Hexadecimal 5. The addition of two decimal digits in BCD can be
b) Binary coded done through ____________
c) Octal a) BCD adder
d) Decimal b) Full adder
c) Ripple carry adder
Answer: b d) Carry look ahead
Explanation: Binary-coded decimal (BCD) is a class
of binary encodings of decimal numbers where each Answer: a
decimal digit is represented by a fixed number of bits, Explanation: The addition of two decimal digits in
usually four or eight. Hexadecimal and Octal are BCD can be done through BCD adder. Every input
number systems having base 16 and 8 respectively. inserted, in addition by the user converted into binary
and then proceed for the addition. Whereas, Full
2. 29 input circuit will have total of ____________ Adder, Ripple Carry Adder and Carry Look Adder are
a) 32 entries for the addition of binary bits.
b) 128 entries
c) 256 entries 6. 3 bits full adder contains ____________
d) 512 entries a) 3 combinational inputs
b) 4 combinational inputs
Answer: d c) 6 combinational inputs
Explanation: 29 input circuit would have d) 8 combinational inputs
512(2*2*2*2*2*2*2*2*2 = 512) entries.
Answer: d
3. BCD adder can be constructed with 3 IC packages Explanation: 3 bits full adder contains 23 = 8
each of ____________ combinational inputs.
a) 2 bits
b) 3 bits 7. The simplified expression of full adder carry is
c) 4 bits ____________
d) 5 bits a) c = xy+xz+yz
b) c = xy+xz
Answer: c c) c = xy+yz
Explanation: Binary-coded decimal (BCD) is a class d) c = x+y+z
of binary encodings of decimal numbers where each
decimal digit is represented by a fixed number of bits, Answer: a
usually four or eight. BCD adder can be constructed Explanation: A full adder is a combinational circuit
with 3 IC packages. Each of 4-bit adders is an having 3 inputs and 2 outputs, namely SUM and
MSI(Medium scale Integration) function and 3 gates CARRY. The simplified expression of full adder carry
for the correction logic need one SSI (Small Scale is c = xy+xz+yz.
Integration) package.
8. Complement of F’ gives back __________
a) F’
b) F 2. The addition 1+1 gives 0 as a result.
c) FF a) True
d) FF’ b) False
Answer: b Answer: a
Explanation: Complement means inversion. So, Explanation: The two result obtained is 0 with a carry
complement of F’ gives back F, as per the Law of of 1. This carry is transferred to the next higher
Involution. column.
9. Decimal digit in BCD can be represented by 3. The result of 0*1 in binary is ____________
____________ a) 0
a) 1 input line b) 1
b) 2 input lines c) invalid
c) 3 input lines d) 10
d) 4 input lines
Answer: a
Answer: d Explanation: The binary multiplication of any number
Explanation: Binary-coded decimal (BCD) is a class with 0 will give the result 0 itself. Any binary number
of binary encodings of decimal numbers where each when multiplied by 0 gives 0 only. e.g. 1101 * 0000 =
decimal digit is represented by a fixed number of bits, 0000.
usually four or eight. Decimal digit in BCD can be
represented by 4 input lines. Since it is constructed 4. The multiplication of 110 * 111 is performed. What
with 4-bits. is a general term used for 111?
a) Dividend
10. The number of logic gates and the way of their b) Quotient
interconnections can be classified as ____________ c) Multiplicand
a) Logical network d) Multiplier
b) System network
c) Circuit network Answer: d
d) Gate network Explanation: 111 is called the multiplier.
Whenever a multiplication is performed the second
Answer: a term is called the multiplier whereas the first term is
Explanation: The number of different levels of logic called the multiplicand.
gates is represented in a fashion which is known as a
logical network. 5. The result obtained on binary multiplication of 1010
* 1100 is _____________
a) 0001111
TOPIC 2.6 BINARY MULTIPLIER b) 0011111
c) 1111100
1. Perform binary addition of 1101 + 0010 is d) 1111000
________
a) 1110 Answer: d
b) 1111 Explanation: The solution is as follows :
c) 0111
1010
d) 1,1101 * 1100
________
Answer: b 0000
Explanation: The addition is performed as : 0000
1101 1010
+ 0010 1010
_______
_______ 1111000
1111
Therefore, the result is 1111. 6. Which of the following is often called the double
precision format?
a) 64-bit
b) 8-bit rest of the bits are magnitude bits. So the number is:
c) 32-bit 01010 =23 * 1 + 21 * 1 =8+2 =10.
d) 128-bit But , the sign bit is 1,
Therefore the answer is : (-2)10.
Answer: a
Explanation: The 64-bit format is referred to as the
double precision format. It has 1 sign bit, 8 exponent TOPIC 2.7 MAGNITUDE
bits and 23 bits for the mantissa. COMPARATOR
7. What do you call the intermediate terms in binary
multiplication? 1. All the comparisons made by comparator is done
a) Multipliers using ____________
b) Mid terms a) 1 circuit
c) Partial Products b) 2 circuits
d) Multiplicands c) 3 circuits
d) 4 circuits
Answer: c
Explanation: The intermediate terms are called partial Answer: a
terms. The mid terms obtained in the binary Explanation: A comparator is a combinational circuit
multiplications are the partial ones whereas the answer that takes two numbers as input in binary form and
obtained is called the final product. results whether one input is greater, lesser or equal to
the other input. Because, all the input is compared to
8. The result that is smaller than the smallest number each other, therefore it is possible only by using 1
obtained is referred to as ___________ circuit.
a) NaN
b) Underflow 2. One that is not the outcome of magnitude
c) Smallest comparator is ____________
d) Mantissa a) a > b
b) a – b
Answer: b c) a < b
Explanation: It is referred to as underflow. Nan stands d) a = b
for not a number. Mantissa is the part after the
decimal. Answer: b
Explanation: A comparator is a combinational circuit
9. The number of sign bits in a 32-bit IEEE format is that takes two numbers as input in binary form and
_______ results whether one input is greater, lesser or equal to
a) 1 the other input. In a digital comparator, only 3 outputs
b) 11 are possible (i.e. A = B, A > B, A < B). So, a – b is
c) 9 incorrect option.
d) 23
3. If two numbers are not equal then binary variable
Answer: a will be ____________
Explanation: There is only 1 sign bit in all the a) 0
standards. In a 32-bit format, there is 1 sign bit, 8 bits b) 1
for the exponent and 23 bits for the mantissa. c) A
d) B
10. Express the decimal format of the signed binary
number (101010)2 . Answer: a
a) 10 Explanation: A comparator is a combinational circuit
b) 12 that takes two numbers as input in binary form and
c) -12 results whether one input is greater, lesser or equal to
d) -10 the other input. In a digital comparator, only 3 outputs
are possible (i.e. A = B, A >B, A < B). Other than this,
Answer: d the output will be 0.
Explanation: The first bit is the sign bit whereas the
4. How many inputs are required for a digital 8. A circuit that compares two numbers and determine
comparator? their magnitude is called ____________
a) 1 a) Height comparator
b) 2 b) Size comparator
c) 3 c) Comparator
d) 4 d) Magnitude comparator
Answer: a Answer: d
Explanation: A comparator is a combinational circuit Explanation: A comparator is a combinational circuit
that takes two numbers as input in binary form and that takes two numbers as input in binary form and
results whether one input is greater, lesser or equal to results whether one input is greater, lesser or equal to
the other input. Thus, there are two inputs required for the other input. A circuit that compares two numbers
a digital comparator (i.e. A & B). and determine their magnitude is called magnitude
comparator.
5. In a comparator, if we get input as A>B then the
output will be ____________ 9. A procedure that specifies finite set of steps is called
a) 1 ____________
b) 0 a) Algorithm
c) A b) Flow chart
d) B c) Chart
d) Venn diagram
Answer: a
Explanation: A comparator is a combinational circuit Answer: a
that takes two numbers as input in binary form and Explanation: A procedure that specifies finite set of
results whether one input is greater, lesser or equal to steps is called algorithm, While a flowchart is a
the other input. If A > B, it means that it satisfies one pictorial representation of the algorithm.
of the condition among three. Hence the output will be
1. 10. How many types of digital comparators are?
a) 1
6. Which one is a basic comparator? b) 2
a) XOR c) 3
b) XNOR d) 4
c) AND
d) NAND Answer: b
Explanation: There are two main types of Digital
Answer: a Comparator available and these are: Identity
Explanation: Generally, an XNOR outputs high for Comparator & Magnitude Comparator. Identity
even number of 1s or all 0s and outputs low for Comparator checks only the equality of the inputs and
otherwise. Thus, an XNOR gate is a basic comparator, thus has one output terminal. While Magnitude
because its output is “1” only if its two input bits are Comparator checks for greater than, less than as well
equal. as equality of the inputs, and thus has 3 output
terminals.
7. Comparators are used in ____________
a) Memory 11. An identify comparator is defined as a digital
b) CPU comparator which has ____________
c) Motherboard a) Only one output terminal
d) Hard drive b) Two output terminals
c) Three output terminals
Answer: b d) No output terminal
Explanation: Comparators are used in central
processing unit (CPUs). Because all the arithmetic and Answer: a
logical operations are performed in the Explanation: An Identity Comparator is a digital
ALU(Arithmetic Logic Unit) part of the CPU. comparator that has only one output terminal for when
A = B either “HIGH” A = B = 1 or “LOW” A = B = 0.

12. A magnitude comparator is defined as a digital input. Thus, a Decimal-to-bcd converter has decimal
comparator which has ____________ values as inputs which range from 0-9. So, total 10
a) Only one output terminal inputs are there in a decimal-to-BCD encoder.
b) Two output terminals
c) Three output terminals 2. How many outputs will a decimal-to-BCD encoder
d) No output terminal have?
a) 4
Answer: c b) 8
Explanation: A Magnitude Comparator is a digital c) 12
comparator which has three output terminals, one each d) 16
for equality, A = B greater than, A > B and less than A
< B. Answer: a
Explanation: An encoder is a combinational circuit
13. The purpose of a Digital Comparator is encoding the information of 2n input lines to n output
____________ lines, thus producing the binary equivalent of the
a) To convert analog input into digital input. Thus, a decimal to BCD encoder has 4 outputs.
b) To create different outputs
c) To add a set of different numbers 3. How is an encoder different from a decoder?
d) To compare a set of variables or unknown numbers a) The output of an encoder is a binary code for 1-of-N
input
Answer: d b) The output of a decoder is a binary code for 1-of-N
Explanation: A comparator is a combinational circuit input
that takes two numbers as input in binary form and c) The output of an encoder is a binary code for N-of-1
results whether one input is greater, lesser or equal to output
the other input. The purpose of a Digital Comparator is d) The output of a decoder is a binary code for N-of-1
to compare a set of variables or unknown numbers, for output
example A (A1, A2, A3, …. An, etc) against that of a
constant or unknown value such as B (B1, B2, B3, …. Answer: a
Bn, etc) and produce an output condition or flag Explanation: An encoder is a combinational circuit
depending upon the result of the comparison. encoding the information of 2n input lines to n output
lines, thus producing the binary equivalent of the
14. TTL 74LS85 is a _____________
input. It performs the opposite operation of a decoder
a) 1-bit digital comparator
b) 4-bit magnitude comparator which results in 2n outputs from n inputs. Thus, an
c) 8-bit magnitude comparator encoder different from a decoder because of the output
d) 8-bit word comparator of an encoder is a binary code for 1-of-N input.
Answer: b 4. If we record any music in any recorder, such types

Explanation: TTL 74LS85 is a 4-bit magnitude of process is called ___________
comparator. a) Multiplexing
b) Encoding
c) Decoding
TOPIC 2.8 ENCODERS & DECODERS d) Demultiplexing
1. How many inputs will a decimal-to-BCD encoder Answer: b

have? Explanation: If we record any music in any recorder,
a) 4 it means that we are giving data to a recorder. So, such
b) 8 process is called encoding. Getting back the music
c) 10 from the recorded data, is known as decoding.
d) 16
5. Can an encoder be a transducer?
Answer: c a) Yes
Explanation: An encoder is a combinational circuit b) No
c) May or may not be
encoding the information of 2n input lines to n output
d) Both are not even related slightly
Answer: a c) 4
Explanation: Of course, a transducer is a device d) 2^4
which has the capability to emit data as well as to
accept. Transducer converts signal from one form of Answer: b
energy to another. Explanation: An encoder is a combinational circuit
encoding the information of 2n input lines to n output
6. How many OR gates are required for a Decimal-to- lines, thus producing the binary equivalent of the
bcd encoder?
input. There are 28 combinations are possible for an 8-
a) 2
bit input encoder but out of which only 8 are used
b) 10
using 3 output lines. It is a disadvantage of encoder.
c) 3
d) 4 9. The discrepancy of 0 output due to all inputs being 0
or D0, being 0 is resolved by using additional input
Answer: d
known as ___________
a) Enable
encoding the information of 2^n input lines to n output
b) Disable
c) Strobe
input.
d) Clock
This is clear from the diagram that it requires 4 OR
gates: Answer: a
Explanation: Such problems are resolved by using
enable input, which behaves as active if it gets 0 as
input since it is an active-low pin.
10. Can an encoder be called as multiplexer?

a) No
b) Yes
c) Sometimes
d) Never
Answer: b
Explanation: A multiplexer or MUX is a combination
circuit that contains more than one input line, one
output line and more than one selection line. Whereas,
. an encoder is also considered a type of multiplexer but
without a single output line and without any selection
7. How many OR gates are required for an octal-to- lines.
binary encoder?
a) 3 11. If two inputs are active on a priority encoder,
b) 2 which will be coded on the output?
c) 8 a) The higher value
d) 10 b) The lower value
c) Neither of the inputs
Answer: a d) Both of the inputs
encoding the information of 2n input lines to n output Answer: a
lines, thus producing the binary equivalent of the Explanation: An encoder is a combinational circuit
input. Thus, in octal to binary encoder there are 8 encoding the information of 2n input lines to n output
(=23) inputs, thus 3 output lines. lines, thus producing the binary equivalent of the
input. If two inputs are active on a priority encoder, the
8. For 8-bit input encoder how many combinations are input of higher value will be coded in the output.
possible?
a) 8 TOPIC 2.9 MULTIPLEXERS
b) 2^8

1. What is a multiplexer? Answer: c
a) It is a type of decoder which decodes several inputs Explanation: The major functioning responsibility of
and gives one output the multiplexing combinational circuit is generation of
b) A multiplexer is a device which converts many selected path between multiple sources and a single
signals into one destination because it makes the circuit too flexible. A
c) It takes one input and results into many output multiplexer (or MUX) is a device that selects one of
d) It is a type of encoder which decodes several inputs several analog or digital input signals and forwards the
and gives one output selected input into a single line, depending on the
active select lines.
Answer: b
Explanation: A multiplexer (or MUX) is a device that 5. What is the function of an enable input on a
selects one of several analog or digital input signals multiplexer chip?
and forwards the selected input into a single line, a) To apply Vcc
depending on the active select lines. b) To connect ground
c) To active the entire chip
2. Which combinational circuit is renowned for d) To active one half of the chip
selecting a single input from multiple inputs &
directing the binary information to output line? Answer: c
a) Data Selector Explanation: Enable input is used to active the chip,
b) Data distributor when enable is high the chip works (ACTIVE), when
c) Both data selector and data distributor enable is low the chip does not work (MEMORY).
d) DeMultiplexer However, Enable can be Active-High or Active-Low,
indicating it is active either when it is connected to
Answer: a VCC or GND respectively.
Explanation: Data Selector is another name of
Multiplexer. A multiplexer (or MUX) is a device that 6. One multiplexer can take the place of ___________
selects one of several analog or digital input signals a) Several SSI logic gates
and forwards the selected input into a single line, b) Combinational logic circuits
depending on the active select lines. c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic
3. It is possible for an enable or strobe input to circuits
undergo an expansion of two or more MUX ICs to the
digital multiplexer with the proficiency of large Answer: d
number of ___________ Explanation: A multiplexer (or MUX) is a device that
a) Inputs selects one of several analog or digital input signals
b) Outputs and forwards the selected input into a single line,
c) Selection lines depending on the active select lines. Since many
d) Enable lines operational behaviour can be performed by using a
multiplexer. Whereas, a combinational circuit is a
Answer: a combination of many logic gates which makes the
Explanation: It is possible for an enable or strobe circuit more complex.
input to undergo an expansion of two or more MUX
ICs to the digital multiplexer with the proficiency of 7. A digital multiplexer is a combinational circuit that
large number of inputs. selects ___________
a) One digital information from several sources and
4. Which is the major functioning responsibility of the transmits the selected one
multiplexing combinational circuit? b) Many digital information and convert them into one
a) Decoding the binary information c) Many decimal inputs and transmits the selected
b) Generation of all minterms in an output function information
with OR-gate d) Many decimal outputs and accepts the selected
c) Generation of selected path between multiple information
sources and a single destination
d) Encoding of binary information Answer: a
Explanation: A digital multiplexer is a combinational
circuit that selects one digital information from several
sources and transmits the selected information on a around 10 digits out of which one is selected one at a
single output line depending on the status of the select time and fed to the output.
lines. That is why it is also known as a data selector.
12. How many NOT gates are required for the
8. In a multiplexer, the selection of a particular input construction of a 4-to-1 multiplexer?
line is controlled by ___________ a) 3
a) Data controller b) 4
b) Selected lines c) 2
c) Logic gates d) 5
d) Both data controller and selected lines
Answer: c
Answer: b Explanation: There are two NOT gates required for
Explanation: The selection of a particular input line is the construction of 4-to-1 multiplexer. x0, x1, x2 and
controlled by a set of selected lines in a multiplexer, x3 are the inputs and C1 and C0 are the select lines
which helps to select a particular input from several and M is the output.
sources. The diagram of a 4-to-1 multiplexer is shown below:
9. If the number of n selected input lines is equal to

2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) 2n
Answer: b
Explanation: If the number of n selected input lines is
equal to 2^m then it requires m select lines to select
one of m select lines.
13. In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1
10. How many select lines would be required for an 8- then the output M is ___________
line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Answer: d
Explanation: 2n input lines, n control lines and 1
output line available for MUX. Here, 8 input lines
mean 23 inputs. So, 3 control lines are possible.
Depending on the status of the select lines, the input is
selected and fed to the output. a) X0
b) X1
11. A basic multiplexer principle can be demonstrated c) X2
through the use of a ___________ d) X3
a) Single-pole relay
b) DPDT switch Answer: b
c) Rotary switch Explanation: The output will be X1, because c1 = 0
d) Linear stepper and c0 = 1 results into 1 which further results as X1.
And rest of the AND gates gives output as 0.
Answer: c
Explanation: A basic multiplexer principle can be 14. The enable input is also known as ___________
demonstrated through the use of a rotary switch. Since a) Select input
its behaviour is similar to the multiplexer. There are b) Decoded input

c) Strobe does the schematic. So, it is used as documentation,
d) Sink verification and synthesis of large digital designs.
Answer: c 5. The use of VHDL can be done in _____ ways.

Explanation: The enable input is also known as strobe a) 2
which is used to cascade two or more multiplexer ICs b) 3
to construct a multiplexer with a larger number of c) 4
inputs. Enable input activates the multiplexer to d) 5
operate.
Answer: b
Explanation: The VHDL has three coding styles are:
TOPIC 2.10 INTRODUCTION TO HDL (i) data flow, (ii) structural, (iii) behavioural.
1. The full form of HDL is _________________ 6. At high frequencies when the sampling interval is
a) Higher Descriptive Language too long in a frequency counter _____________
b) Higher Definition Language a) The counter works fine
c) Hardware Description Language b) The counter undercounts the frequency
d) High Descriptive Language c) The measurement is less precise
d) The counter overflows
Answer: c
Explanation: The full form of HDL is Hardware Answer: d
Description Language. Explanation: Let the sampling time be 1 sec. This
means the counter will count the number of pulses
2. The full form of VHDL is _____________ from the unknown signal for 1sec duration and would
a) Very High Descriptive Language display it after 1 sec. thus if the signal is of 800 Hz, at
b) Verilog Hardware Description Language the end of 1 sec, counter would have counted up to
c) Variable Definition Language 800. Thus, in case of high frequencies and high
d) None of the Mentioned sampling time, counter might count beyond its limit
and overflows.
Answer: b
Explanation: The full form of VHDL is Verilog 7. The output frequency related to the sampling
Hardware Description Language. interval of a frequency counter as _____________
a) Directly with the sampling interval
3. VHSIC stands for _____________ b) Inversely with the sampling interval
a) Very High Speed Integrated Circuits c) More precision with longer sampling interval
b) Very Higher Speed Integration Circuits d) Less precision with longer sampling interval
c) Variable High Speed Integrated Circuits
d) Variable Higher Speed Integration Circuits Answer: c
Explanation: Sampling interval means a particular
Answer: a frequency range in which the device operates correctly.
Explanation: VHSIC stands for Very High Speed Thus, more precision is produced with longer sampling
Integrated Circuits. interval.
4. VHDL is being used for _____________ 8. In an HDL application of a stepper motor, what is
a) Documentation done next after an up/down counter is built?
b) Verification a) Build the sequencer
c) Synthesis of large digital design b) Test it on a simulator
d) All of the Mentioned c) Test the decoder
d) Design an intermediate integer variable
Answer: d
Explanation: The full form of VHDL is Verilog Answer: b
Hardware Description Language. The acronym of Explanation: Simulator is a software which is used in
VHDL itself captures the entire theme of the language the testing of the stepper motor using up/down counter.
and it describes the hardware in the same manner as

9. In a digital clock application, the basic frequency Answer: d
must be divided down as _____________ Explanation: When a key is pressed the ring counter
a) 1 Hz in the HDL scans the information provided by the user
b) 60 Hz and counts to find the row. The preset state of the ring
c) 100 Hz counter define the proper output of the row encoder.
d) 1000 Hz
14. A major block which is not a part of an HDL
Answer: a frequency counter _____________
Explanation: Minimum count is 1 sec and time = a) Timing and control unit
1/freq. So, t = 1/1 = 1Hz. b) Decoder/display
c) Display register
10. What does the data signal do in the keypad d) Bit shifter
application?
a) The row and column encoded data Answer: d
b) The ring encoded data Explanation: Bit shifter is part of a register in which
c) The freeze locator data bit shifting takes place bit-by-bit either left or right.
d) The ring counter data
15. A stepper motor HDL application must include
Answer: a _____________
Explanation: The data signal arrange the information a) Sequencers and multiplexers
with the help of data flow in row and column manner. b) Types and bits
It encodes the data to be sent. c) Counters and decoders
d) Variables and processes
11. When a key is pressed, what does the ring counter
in the HDL keypad application do? Answer: c
a) Count to find the row Explanation: A stepper motor (also referred to as step
b) Freeze or stepping motor) is an electromechanical device
c) Count to find the column achieving mechanical movements through the
d) Start the D flip-flop conversion of electrical pulses. A stepper motor HDL
application must include counters and decoders for
Answer: a position control. It is tested on the simulator.
Explanation: The data signal arrange the information
with the help of data flow in row and column manner.
It encodes the data to be sent. When a key is pressed TOPIC 2.11 HDL MODELS OF
the ring counter in the HDL scans the information COMBINATIONAL CIRCUITS
provided by the user and counts to find the row.
1. Which of the following is a not a characteristics of
12. A step which should be followed in project combinational circuits?
management is known as _____________ a) The output of combinational circuit depends on
a) Overall definition present input
b) System documentation b) There is no use of clock signal in combinational
c) Synthesis and testing circuits
d) System integration c) The output of combinational circuit depends on
previous output
Answer: b d) There is no storage element in combinational circuit
Explanation: System documentation is the second step
of project management in which a result of the system Answer: c
is noted simultaneously. Explanation: A combinational circuit is the one which
has no storage of previous output. The next state or
13. In the keypad application, the preset state of the output of the combinational circuit depends only on its
ring counter define _____________ present input and hence no clock signal is required.
a) The NANDing of the columns
b) The NANDing of the rows 2. Sequential code can’t be used to design
c) The proper output of the column encoder combinational circuit.
d) The proper output of the row encoder

a) True a) L2
b) False b) L3
c) L4
Answer: b d) No error
Explanation: There is no restriction on usage of any
kind of statements while realizing a combinational Answer: d
circuit. Combinational circuit may be implemented by Explanation: There is no error in the given piece of
using statements like IF, CASE etc. the code. However, there was no need to use WHEN in
the line L4 because there is no other case to be
3. Which of the following is not a combinational selected from many inputs. Last case can be directly
circuit? expressed without any use of WHEN.
a) Adder
b) Code convertor 6. In a given combinational circuit, the concurrent
c) Multiplexer statements are used with selected assignments using
d) Counter WHEN and ELSE keyword. What is the other
alternative to implement the same?
Answer: d a) WITH-SELECT
Explanation: Since counter makes use of either clock b) WITH-SELECT-WHEN
signal or previous output to determine next state. c) IF-ELSE
Therefore, counter is a sequential circuit and all the d) CASE
others like multiplexer, adder and code convertors are
the examples of combinational circuit. Answer: b
Explanation: Because only concurrent statements can
4. The code given below is a VHDL implementation of be used, therefore, WITH-SELECT is the correct
_________ alternative for the method used by the user. But,
WITH-SELECT also requires WHEN keyword to
ARCHITECTURE my_circuit OF my_logic IS implement the selected assignment.
BEGIN
WITH ab SELECT
y <= x0 WHEN “00”; 7. Which of the following entity declares the ports of a
x1 WHEN “01”; 3 by 8 decoder?
x2 WHEN “10”; a)
x3 WHEN “11”;
END my_circuit; ENTITY decoder IS
PORT( inp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a) 4 to 1 MUX Outp: OUT STD_LOGIC_VECTOR(8 DOWNT
b) 1 to 4 DEMUX END decoder;
c) 8 to 1 MUX
d) 1 to 8 DEMUX b)
ENTITY decoder IS
Answer: a PORT( inp : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
Explanation: In the given architecture, the output is Outp: OUT STD_LOGIC_VECTOR(3 DOWNT
single (y), which is selected with the help of a and b. END decoder;
So, a and b are select lines and y is the output which is
selected from 4 inputs. Therefore, it is the multiplexer c)
circuit with 4 inputs and 1 output.
ENTITY decoder IS
5. Which of the following line of the code contains an
Outp: OUT STD_LOGIC_VECTOR(2 DOWNT
error? END decoder;
L1: ARCHITECTURE mux1 OF mux IS d)

L2: BEGIN
L3: y<= x0 WHEN x = ‘0’ ELSE
ENTITY decoder IS
L4: <= x1 WHEN x = ‘1’;
L5: END mux1;
Outp: OUT STD_LOGIC_VECTOR(7 DOWNT
END decoder;

Answer: d inputs and both are of vector type. There is one vector
Explanation: In a 3 by 8 decoder, there must be 3 output and another single bit output. Therefore, it has
inputs and 8 outputs. For 3 inputs the dimension of to be an adder, but because 4 bits are there in the input
vector must be 2 DOWNTO 0 and for output the and output so it is a 4-bit parallel adder.
dimensions should be 7 DOWNTO 0. Therefore,
option d is the correct port entity of the 3 by 8 decoder.
UNIT III SYNCHRONOUS

8. For using a process to implement a combinational
circuit, which signals should be in the sensitivity list?
SEQUENTIAL LOGIC
a) Inputs of the circuit
b) Outputs of the circuit TOPIC 3.1 SEQUENTIAL CIRCUIT
c) Both of the Inputs and Outputs
(FLIP-FLOPS)
d) No signal should be in the sensitivity list
Answer: a 1. Latches constructed with NOR and NAND gates

Explanation: In a process used for the implementation tend to remain in the latched condition due to which
of the combinational circuit, all the input signals used configuration feature?
which are to be read, should appear in its sensitivity a) Low input voltages
list. In a combinational circuit, there can be many b) Synchronous operation
inputs and those inputs should appear in the sensitivity c) Gate impedance
list of the process. d) Cross coupling
9. A 4 to 16 decoder can be used as a code converter. Answer: d

What will be the inputs and outputs of the converter Explanation: Latch is a type of bistable multivibrator
respectively? having two stable states. Both inputs of a latch are
a) Binary, Octal directly connected to the other’s output. Such types of
b) Octal, Binary structure is called cross coupling and due to which
c) Hexadecimal, Binary latches remain in the latched condition.
d) Binary, Hexadecimal
2. One example of the use of an S-R flip-flop is as
Answer: c ___________
Explanation: Since, 24 = 16, therefore, the decoder a) Transition pulse generator
can act as hexadecimal to binary converter. Because, 4 b) Racer
bits input is converted to 16 bits output. Each bit c) Switch debouncer
corresponding to 4 output bits. So, clearly it is a d) Astable oscillator
hexadecimal to binary convertor.
Answer: c
10. Following entity may represent a ________ circuit. Explanation: The SR flip-flop is very effective in
removing the effects of switch bounce, which is the
ENTITY my_circuit IS unwanted noise caused during the switching of
PORT (a, b : IN STD_LOGIV_VECTOR(3 DOWNTO 0); electronic devices.
x : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
y : OUT STD_LOGIC); 3. The truth table for an S-R flip-flop has how many
END my_circuit;
VALID entries?
a) Half adder a) 1
b) Full adder b) 2
c) Multiplexer c) 3
d) Parallel adder d) 4
Answer: d Answer: c
Explanation: The entity gives information about Explanation: The SR flip-flop actually has three
inputs and outputs of the circuit. The circuit has two inputs, Set, Reset and its current state. The Invalid or
Undefined State occurs at both S and R being at 1.
4. When both inputs of a J-K flip-flop cycle, the output are fed back to the input side. So, The circuits whose
will ___________ outputs at any instant of time depends only on the
a) Be invalid present input but also on the past outputs are called
b) Change sequential circuits. Unlike sequential circuits, if output
c) Not change depends only on the present state, then it’s known as
d) Toggle combinational circuits.
Answer: c 8. Whose operations are more faster among the

Explanation: After one cycle the value of each input following?
comes to the same value. Eg: Assume J=0 and K=1. a) Combinational circuits
After 1 cycle, it becomes as J=0->1->0(1 cycle b) Sequential circuits
complete) and K=1->0->1(1 cycle complete). The J & c) Latches
K flip-flop has 4 stable states: Latch, Reset, Set and d) Flip-flops
Toggle.
Answer: a
5. Which of the following is correct for a gated D-type Explanation: Combinational circuits are often faster
flip-flop? than sequential circuits. Since, the combinational
a) The Q output is either SET or RESET as soon as the circuits do not require memory elements whereas the
D input goes HIGH or LOW sequential circuits need memory devices to perform
b) The output complement follows the input when their operations in sequence. Latches and Flip-flops
enabled come under sequential circuits.
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH 9. How many types of sequential circuits are?
a) 2
Answer: a b) 3
Explanation: In D flip flop, when the clock is high c) 4
then the output depends on the input otherwise d) 5
reminds previous output. In a state of clock high, when
D is high the output Q also high, if D is ‘0’ then output Answer: a
is also zero. Like SR flip-flop, the D-flip-flop also Explanation: There are two type of sequential circuits
have an invalid state at both inputs being 1. viz., (i) synchronous or clocked and (ii) asynchronous
or unclocked. Synchronous Sequential Circuits are
6. A basic S-R flip-flop can be constructed by cross- triggered in the presence of a clock signal, whereas,
coupling of which basic logic gates? Asynchronous Sequential Circuits function in the
a) AND or OR gates absence of a clock signal.
b) XOR or XNOR gates
c) NOR or NAND gates 10. The sequential circuit is also called ___________
d) AND or NOR gates a) Flip-flop
b) Latch
Answer: c c) Strobe
Explanation: The basic S-R flip-flop can be d) Adder
constructed by cross coupling of NOR or NAND
gates. Cross coupling means the output of second gate Answer: b
is fed to the input of first gate and vice-versa. Explanation: The sequential circuit is also called a
latch because both are a memory cell, which are
7. The logic circuits whose outputs at any instant of capable of storing one bit of information.
time depends only on the present input but also on the
past outputs are called 11. The basic latch consists of ___________
a) Combinational circuits a) Two inverters
b) Sequential circuits b) Two comparators
c) Latches c) Two amplifiers
d) Flip-flops d) Two adders
Answer: b Answer: a
Explanation: In sequential circuits, the output signals Explanation: The basic latch consists of two inverters.

It is in the sense that if the output Q = 0 then the 1. A latch is an example of a ___________
second output Q’ = 1 and vice versa. a) Monostable multivibrator
b) Astable multivibrator
12. In S-R flip-flop, if Q = 0 the output is said to be c) Bistable multivibrator
___________ d) 555 timer
a) Set
b) Reset Answer: c
c) Previous state Explanation: A latch is an example of a bistable
d) Current state multivibrator. A Bistable multivibrator is one in which
the circuit is stable in either of two states. It can be
Answer: b flipped from one state to the other state and vice-versa.
Explanation: In S-R flip-flop, if Q = 0 the output is
said to be reset and set for Q = 1. 2. Latch is a device with ___________
a) One stable state
13. The output of latches will remain in set/reset untill b) Two stable state
___________ c) Three stable state
a) The trigger pulse is given to change the state d) Infinite stable states
b) Any pulse given to go into previous state
c) They don’t get any pulse more Answer: b
d) The pulse is edge-triggered Explanation: Since, a latch works on the principal of
bistable multivibrator. A Bistable multivibrator is one
Answer: a in which the circuit is stable in either of two states. It
Explanation: The output of latches will remain in can be flipped from one state to the other state and
set/reset untill the trigger pulse is given to change the vice-versa. So a latch has two stable states.
state.
3. Why latches are called a memory devices?
14. What is a trigger pulse? a) It has capability to stare 8 bits of data
a) A pulse that starts a cycle of operation b) It has internal memory of 4 bit
b) A pulse that reverses the cycle of operation c) It can store one bit of data
c) A pulse that prevents a cycle of operation d) It can store infinite amount of data
d) A pulse that enhances a cycle of operation
Answer: c
Answer: a Explanation: Latches can be memory devices, and can
Explanation: Trigger pulse is defined as a pulse that store one bit of data for as long as the device is
starts a cycle of operation. powered. Once device is turned off, the memory gets
refreshed.
15. The circuits of NOR based S-R latch classified as
asynchronous sequential circuits, why? 4. Two stable states of latches are ___________
a) Because of inverted outputs a) Astable & Monostable
b) Because of triggering functionality b) Low input & high output
c) Because of cross-coupled connection c) High output & low output
d) Because of inverted outputs & triggering d) Low output & high input
functionality
Answer: c
Answer: c Explanation: A latch has two stable states, following
Explanation: The cross-coupled connections from the the principle of Bistable Multivibrator. There are two
output of one gate to the input of the other gate stable states of latches and these states are high-output
constitute a feedback path. For this reason, the circuits and low-output.
of NOR based S-R latch classified as asynchronous
sequential circuits. Moreover, they are referred to as 5. How many types of latches are ___________
asynchronous because they function in the absence of a) 4
a clock pulse. b) 3
c) 2
d) 5
TOPIC 3.2 LATCHES

Answer: a and q’. It is clear from the diagram:
Explanation: There are four types of latches: SR latch,
D latch, JK latch and T latch. D latch is a modified
form of SR latch whereas, T latch is an advanced form
of JK latch.
6. The full form of SR is ___________

a) System rated
b) Set reset
c) Set ready .
d) Set Rated
9. The NAND latch works when both inputs are
Answer: b ___________
Explanation: The full form of SR is set/reset. It is a a) 1
type of latch having two stable states. b) 0
c) Inverted
7. The SR latch consists of ___________ d) Don’t cares
a) 1 input
b) 2 inputs Answer: a
c) 3 inputs Explanation: The NAND latch works when both
d) 4 inputs inputs are 1. Since, both of the inputs are inverted in a
NAND latch.
Answer: b
Explanation: SR or Set-Reset latch is the simplest 10. The first step of analysis procedure of SR latch is
type of bistable multivibrator having two stable states. to ___________
The diagram of SR latch is shown below: a) label inputs
b) label outputs
c) label states
d) label tables
Answer: b
Explanation: All flip flops have at least one output
labeled Q (i.e. inverted). This is so because the flip
flops have inverting gates inside them, hence in order
to have both Q and Q complement available, we have
atleast one output labelled.
8. The outputs of SR latch are ___________
a) x and y 11. The inputs of SR latch are ___________
b) a and b a) x and y
c) s and r b) a and b
d) q and q’ c) s and r
d) j and k
Answer: d
Explanation: SR or Set-Reset latch is the simplest Answer: c
type of bistable multivibrator having two stable states. Explanation: SR or Set-Reset latch is the simplest
The inputs of SR latch are s and r while outputs are q type of bistable multivibrator having two stable states.
The inputs of SR latch are s and r while outputs are q

and q’. It is clear from the diagram: information
d) The group of flip-flops suitable for storing binary
information
Answer: d
Explanation: A register is defined as the group of flip-
flops suitable for storing binary information. Each flip-
flop is a binary cell capable of storing one bit of
information. The data in a register can be transferred
from one flip-flop to another.
12. When a high is applied to the Set line of an SR 2. The register is a type of ___________
latch, then ___________ a) Sequential circuit
a) Q output goes high b) Combinational circuit
b) Q’ output goes high c) CPU
c) Q output goes low d) Latches
d) Both Q and Q’ go high
Answer: a
Answer: a Explanation: Register’s output depends on the past
Explanation: S input of a SR latch is directly and present states of the inputs. The device which
connected to the output Q. So, when a high is applied follows these properties is termed as a sequential
Q output goes high and Q’ low. circuit. Whereas, combinational circuits only depend
on the present values of inputs.
13. When both inputs of SR latches are low, the latch
___________ 3. How many types of registers are?
a) Q output goes high a) 2
b) Q’ output goes high b) 3
c) It remains in its previously set or reset state c) 4
d) it goes to its next set or reset state d) 5
Answer: c Answer: c
Explanation: When both inputs of SR latches are low, Explanation: There are 4 types of shift registers, viz.,
the latch remains in it’s present state. There is no Serial-In/Serial-Out, Serial-In/Parallel-Out, Parallel-
change in the output. In/Serial-Out and Parallel-In/Parallel-Out.
14. When both inputs of SR latches are high, the latch 4. The main difference between a register and a
goes ___________ counter is ___________
a) Unstable a) A register has no specific sequence of states
b) Stable b) A counter has no specific sequence of states
c) Metastable c) A register has capability to store one bit of
d) Bistable information but counter has n-bit
d) A register counts data
Answer: c
Explanation: When both gates are identical and this is Answer: a
“metastable”, and the device will be in an undefined Explanation: The main difference between a register
state for an indefinite period. and a counter is that a register has no specific sequence
of states except in certain specialised applications.
TOPIC 3.3 REGISTERS
5. In D register, ‘D’ stands for ___________
a) Delay
1. A register is defined as ___________ b) Decrement
a) The group of latches for storing one bit of c) Data
information d) Decay
b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of

Answer: c Answer: a
Explanation: D stands for “data” in case of flip-flops Explanation: There are two types of shifting of data
and not delay. Registers are made of a group of flip- are available and these are serial shifting & parallel
flops. shifting.
6. Registers capable of shifting in one direction is 10. In serial shifting method, data shifting occurs
___________ ____________
a) Universal shift register a) One bit at a time
b) Unidirectional shift register b) simultaneously
c) Unipolar shift register c) Two bit at a time
d) Unique shift register d) Four bit at a time
Answer: b Answer: a
Explanation: The register capable of shifting in one Explanation: As the name suggests serial shifting, it
direction is unidirectional shift register. The register means that data shifting will take place one bit at a
capable of shifting in both directions is known as a time for each clock pulse in a serial fashion. While in
bidirectional shift register. parallel shifting, shifting will take place with all bits
simultaneously for each clock pulse in a parallel
7. A register that is used to store binary information is fashion.
called ___________
a) Data register
b) Binary register TOPIC 3.4 COUNTERS
c) Shift register
d) D – Register 1. In digital logic, a counter is a device which
____________
Answer: b a) Counts the number of outputs
Explanation: A register that is used to store binary b) Stores the number of times a particular event or
information is called a binary register. A register in process has occurred
which data can be shifted is called shift register. c) Stores the number of times a clock pulse rises and
falls
8. A shift register is defined as ___________ d) Counts the number of inputs
a) The register capable of shifting information to
another register Answer: b
b) The register capable of shifting information either to Explanation: In digital logic and computing, a counter
the right or to the left is a device which stores (and sometimes displays) the
c) The register capable of shifting information to the number of times a particular event or process has
right only occurred, often in relationship to a clock signal.
d) The register capable of shifting information to the
left only 2. A counter circuit is usually constructed of
____________
Answer: b a) A number of latches connected in cascade form
Explanation: The register capable of shifting b) A number of NAND gates connected in cascade
information either to the right or to the left is termed as form
shift register. A register in which data can be shifted c) A number of flip-flops connected in cascade
only in one direction is called unidirectional shift d) A number of NOR gates connected in cascade form
register, while if data can shifted in both directions, it
is known as a bidirectional shift register. Answer: c
Explanation: A counter circuit is usually constructed
9. How many methods of shifting of data are of a number of flip-flops connected in cascade.
available? Preferably, JK Flip-flops are used to construct counters
a) 2 and registers.
b) 3
c) 4 3. What is the maximum possible range of bit-count
d) 5 specifically in n-bit binary counter consisting of ‘n’
number of flip-flops?
a) 0 to 2n Answer: c
Explanation: Synchronous Counter is a Medium Scale
b) 0 to 2n + 1
Integrated (MSI). In Synchronous Counters, the clock
c) 0 to 2n – 1 pulse is supplied to all the flip-flops simultaneously.
d) 0 to 2n+1/2
8. Three decade counter would have ____________
Answer: c a) 2 BCD counters
Explanation: The maximum possible range of bit- b) 3 BCD counters
count specifically in n-bit binary counter consisting of c) 4 BCD counters
‘n’ number of flip-flops is 0 to 2n-1. For say, there is a d) 5 BCD counters
2-bit counter, then it will count till 22-1 = 3. Thus, it
Answer: b
will count from 0 to 3.
Explanation: Three decade counter has 30 states and a
4. How many types of the counter are there? BCD counter has 10 states. So, it would require 3 BCD
a) 2 counters. Thus, a three decade counter will count from
b) 3 0 to 29.
c) 4
9. BCD counter is also known as ____________
d) 5
a) Parallel counter
Answer: b b) Decade counter
Explanation: Counters are of 3 types, namely, c) Synchronous counter
(i)asynchronous/synchronous, (ii)single and multi- d) VLSI counter
mode & (iii)modulus counter. These further can be
Answer: b
subdivided into Ring Counter, Johnson Counter,
Cascade Counter, Up/Down Counter and such like. Explanation: BCD counter is also known as decade
counter because both have the same number of stages
5. A decimal counter has ______ states. and both count from 0 to 9.
a) 5
10. The parallel outputs of a counter circuit represent
b) 10
the _____________
c) 15
a) Parallel data word
d) 20
b) Clock frequency
Answer: b c) Counter modulus
Explanation: Decimal counter is also known as 10 d) Clock count
stage counter. So, it has 10 states. It is also known as
Decade Counter counting from 0 to 9. Answer: d
Explanation: The parallel outputs of a counter circuit
6. Ripple counters are also called ____________ represent the clock count. A counter counts the
a) SSI counters number of times an event takes place in accordance to
b) Asynchronous counters the clock pulse.
c) Synchronous counters
d) VLSI counters TOPIC 3.5 HDL MODELS OF
Answer: b
SEQUENTIAL CIRCUITS
Explanation: Ripple counters are also called
asynchronous counter. In Asynchronous counters, only 1. A sequential logic can’t be executed by concurrent
the first flip-flop is connected to an external clock statements only.
while the rest of the flip-flops have their preceding a) True
flip-flop output as clock to them. b) False
7. Synchronous counter is a type of ____________ Answer: a

a) SSI counters Explanation: It is true that a sequential logic can’t be
b) LSI counters executed by concurrent statements only. It requires the
c) MSI counters sequential statements because they make use of a clock
d) VLSI counters signal.
2. Which of the following sequential circuit doesn’t Answer: c
need a clock signal? Explanation: A process with a clock signal in its
a) Flip flop sensitivity list is called a clocked process. In case of
b) Asynchronous counter sequential logic circuit, one needs a clock signal in the
c) Shift register sensitivity list.
d) Latch
5. Why do we need to define clock signal in the
Answer: d sensitivity list of the process?
Explanation: Latch has an enable input, but no clock a) To trigger the statement as soon as there is some
signal. All other circuits including asynchronous event on clock
counter needs a clock signal. It is called asynchronous b) To trigger the clock signal as soon as there is some
because every flip flop doesn’t have same clock signal. event on input
c) To trigger the clock signal as soon as there is some
3. The following timing diagram shows ______ flip event on output
flop. d) To trigger the statement as soon as there is some
event on input
Answer: a
Explanation: To monitor the events on clock signal,
whether it is positive triggered circuit or negative
triggered circuit, we need to define the clock as a
signal in the sensitivity list. When it is in the
sensitivity list, then every single positive or negative
edge of the signal will trigger the statements inside the
process.
6. A user has designed JK flip flop by using the VHDL

code. The output is continuously switching between 0
and 1. This condition is known as _______
a) Switching condition
b) Master slave condition
c) Race around condition
d) Edge triggered condition
a) T flip-flop Answer: c
b) D flip-flop Explanation: This continuous switching of output
c) SR flip-flop between 0 and 1 may be the result of toggle state of the
d) JK flip-flop flip flop. This occurs when both the inputs J and K are
high and the output toggles its previous state. This
Answer: b condition is called the race around the condition.
Explanation: Since there is only one input to the flip
flop, therefore, it can be either D or T flip flop. But, 7. Which of the following method is not used to
the output becomes equal to the input signal as soon as remove the race around condition in a flip flop?
there is a positive edge of the clock therefore, it is a a) Using level triggered flip flop
delay flip flop. b) Using master slave flip flop
c) Using edge triggered flip flop
4. The process used for implementation of sequential d) All of the above are used to remove the race around
logic in VHDL is called ______ process.
a) Sequential process Answer: a
b) Combinational process Explanation: The race around condition in JK flip flop
c) Clocked process can be removed by two methods which are using edge
d) Unclocked process triggered flip flop and by using master slave flip flop.
However, using level triggered flip flop cause the race
around condition.

8. Which of the following attribute is generally used in c) finite synchronous circuit
implementation of sequential circuits? d) infinite asynchronous circuit
a) ‘STABLE
b) ‘LENGTH Answer: a
c) ‘LAST_EVENT Explanation: Sequential circuits are represented as
d) ‘EVENT finite state machine and may be modelled as
combinational logic.
Answer: d
Explanation: Generally ‘EVENT attribute is used in 2. Sequential circuit includes
implementation of sequential circuits, because a) delays
sequential circuit makes use of clock signal which b) feedback
needs to be detected at every positive or negative edge. c) delays and feedback from input to output
d) delays and feedback from output to input
9. Which of the following line is correct for detecting
positive edge of a clock? Answer: d
a) IF (clk’EVENT AND clk = ‘0’) Explanation: Sequential circuit includes a set of
b) IF (clk’EVENT AND clk = ‘1’) delays and feedback from output to input and it is
c) IF (clk’EVENT OR clk = ‘0’) known as finite state machine.
d) IF (clk’EVENT OR clk = ‘1’)
3. Which constitutes the test vectors in sequential
Answer: b circuits?
Explanation: The correct way to identify the positive a) feedback variables
edge of the clock signal is shown in option b. The b) delay factors
‘EVENT attribute will detect the event and clk = ‘1’ c) test patterns
will check whether its high on clock or not. In this way d) all input combinations
the positive edge is monitored. We need to use AND
operator because both of the conditions should be true. Answer: a
Explanation: The ‘m’ feedback variables constitute
10. A user doesn’t want to use the IF statement for the state vector and determine the maximum number
detecting clock edge. It is possible to do the same by of finite states which may be assumed by the circuit.
using any other keyword in VHDL.
a) True 4. Outputs are functions of
b) False a) present state
b) previous state
Answer: a c) next state
Explanation: It is completely possible to detect the d) present and next state
clock edge (positive or negative) by any other method
than IF statement. One can use the WAIT statement to Answer: a
detect either of the edge of the clock pulse. Explanation: Next state and output are both functions
of present state and the independent inputs.
5. Which is the delay elements for clocked system?

a) AND gates
UNIT IV ASYNCHRONOUS b) OR gates
c) Flip-flops
SEQUENTIAL LOGIC d) Multiplexers
Answer: c
TOPIC 4.1 ANALYSIS AND DESIGN OF Explanation: In clocked systems, the basic delay
ASYNCHRONOUS SEQUENTIAL elements are flip-flops and in asynchronous circuits,
CIRCUITS the delays may be contributed by circuit propagation
delays.
1. Sequential circuits are represented as
6. Which contributes to the necessary delay element?
a) finite state machine
a) flip-flops
b) infinite state machine
b) circuit propagation elements 11. In this iterative test generation method, sequential
c) negative feedback path logic is
d) shift registers a) used in the same pattern
b) converted to test logic
Answer: b c) converted to combinational logic
Explanation: The circuit propagation delays d) converted to asynchronous logic
contribute to the necessary delay elements. The delay
in the feedback path may be non-existence. Answer: c
Explanation: In this iterative test generation method,
7. In an OR gate, if A and B are two inputs and there is the main approach of testing is sequential logic is
struck at 1 fault in B path, then output will be converted into combinational logic by cutting the
a) A feedback lines, thus creating pesudo inputs and
b) 0 outputs.
c) 1
d) B’ 12. For a NAND gate, struck-at 1 fault in second input
line cannot be detected if
Answer: c a) Q is 1
Explanation: In an OR gate, if struck at 1 fault in b) Q is 0
present in B path then output will always be 1. c) Q changes from 1 to 0
d) Q changes from 0 to 1
8. Iterative test generation method suits for circuits
with Answer: b
a) no feedback loops Explanation: In a NAND gate, struck-at 1 fault in the
b) few feedback loops second input line cannot be detected if the output Q is
c) more feedback loops reset (Q=0) prior to applying the test sequence.
d) negative feedback loops only
Answer: b TOPIC 4.2 HAZARDS

Explanation: The iterative test generation methods are
best suited to logic with few feedback loops as in 1. Any condition that causes a processor to stall is
control logic for example. called as _________
a) Hazard
9. Which method is very time consuming? b) Page fault
a) D-algorithm c) System error
b) iterative test generation d) None of the mentioned
c) pseudo exhaustive method
d) test generation pattern Answer: a
Explanation: An hazard causes a delay in the
Answer: b execution process of the processor.
Explanation: Iterative test generation method is time
consuming for circuits of any complexity. It is 2. The periods of time when the unit is idle is called as
necessary to describe the initial states of the circuit, ________
which is also time consuming. a) Stalls
b) Bubbles
10. In this technique, a simple fault manifests into c) Hazards
multiple N faults. d) Both Stalls and Bubbles
a) true
b) false Answer: d
Explanation: The stalls are a type of hazards that
Answer: a affect a pipe-lined system.
Explanation: The main problem in this iterative test
generation technique is that a simple fault in the 3. The contention for the usage of a hardware device is
sequential machine is manifest as N multiple faults called ______
during test. a) Structural hazard
b) Stalk

c) Deadlock c) Optimizing
d) None of the mentioned d) Redundancy
Answer: a Answer: b
Explanation: The processor contends for the usage of Explanation: In a scoreboard, the data dependencies
the hardware and might enter into a deadlock state. of every instruction are logged. Instructions are
released only when the scoreboard determines that
4. The situation wherein the data of operands are not there are no conflicts with previously issued and
available is called ______ incomplete instructions.
a) Data hazard
b) Stock 9. The algorithm followed in most of the systems to
c) Deadlock perform out of order execution is __________
d) Structural hazard a) Tomasulo algorithm
b) Score carding
Answer: a c) Reader-writer algorithm
Explanation: Data hazards are generally caused when d) None of the mentioned
the data is not ready on the destination side.
Answer: a
5. The stalling of the processor due to the Explanation: The Tomasulo algorithm is a hardware
unavailability of the instructions is called as algorithm developed in 1967 by Robert Tomasulo from
___________ IBM. It allows sequential instructions that would
a) Control hazard normally be stalled due to certain dependencies to
b) structural hazard execute non-sequentially (out-of-order execution).
c) Input hazard
d) None of the mentioned 10. The problem where process concurrency becomes
an issue is called as ___________
Answer: a a) Philosophers problem
Explanation: The control hazard also called as b) Bakery problem
instruction hazard is usually caused by a cache miss. c) Bankers problem
d) Reader-writer problem
6. The time lost due to the branch instruction is often
referred to as ____________ Answer: d
a) Latency Explanation: None.
b) Delay To practice all areas of Computer Organization for
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Organisation and Architecture
Answer: c
Explanation: This time also retards the performance
speed of the processor.
7. The pipeline bubbling is a method used to prevent UNIT V MEMORY AND

data hazard and structural hazards.
a) True PROGRAMMABLE LOGIC
b) False
Answer: a
TOPIC 5.1 RAM
Explanation: The periods of time when the unit is idle
is called a Bubble. 1. What is access time?
a) The time taken to move a stored word from one bit
8. ____________ method is used in centralized to other bits after applying the address bits
systems to perform out of order execution. b) The time taken to write a word after applying the
a) Scorecard address bits
b) Score boarding c) The time taken to read a stored word after applying
the address bits

d) The time taken to erase a stored word after applying Answer: a
the address bits Explanation: A Random Access Memory (RAM) is a
volatile chip memory in which both the read and write
Answer: c operations can be performed. Since it is volatile,
Explanation: The access time is the time taken to read therefore it stores data as long as power is on. RAM is
a stored word after applying the address bits in a MOS also known as RWM (i.e. Read Write Memory).
EPROM. It is the time required to fetch data from the
memory. 6. If a RAM chip has n address input lines then it can
access memory locations upto __________
2. What are the typical values of tOE? a) 2(n-1)
a) 10 to 20 ns for bipolar
b) 2(n+1)
b) 25 to 100 ns for NMOS
c) 12 to 50 ns for CMOS c) 2n
d) All of the Mentioned d) 22n
Answer: d Answer: c
Explanation: The access time is the time taken to read Explanation: RAM is a volatile memory, therefore it
a stored word after applying the address bits in a MOS stores data as long as power is on. RAM is also known
EPROM. It is the time required to fetch data from the as RWM (i.e. Read Write Memory). If a RAM chip has
memory. The typical values of tOE (i.e. access time) n address input lines then it can access memory
are 10 to 20 ns for bipolar, 25 to 100 ns for NMOS and locations upto 2n.
12 to 50 ns for CMOS.
7. The n-bit address is placed in the __________
3. Which of the following is not a type of memory? a) MBR
a) RAM b) MAR
b) FPROM c) RAM
c) EEPROM d) ROM
d) ROM
Answer: b
Answer: c Explanation: The n-bit address is placed in the
Explanation: EEPROM (Electrical Erasable
Memory Address Register (MAR) to select one of 2n
Programmable ROM) is not a type of memory because memory locations. It stores the address of the
it is used for erasing purpose only. Through EEPROM,
instruction which is to be executed next.
data can be erased electrically, thereby consuming less
time. 8. Which of the following control signals are selected
for read and write operations in a RAM?
4. The chip by which both the operation of read and
a) Data buffer
write is performed __________
b) Chip select
a) RAM c) Read and write
b) ROM d) Memory
c) PROM
d) EPROM Answer: c
Explanation: Read and write are control signals that
Answer: a
are used to enable memory for read and write
Explanation: A Random Access Memory (RAM) is a
operations respectively.
volatile chip memory in which both the read and write
operations can be performed. Since it is volatile, 9. Computers invariably use RAM for __________
therefore it stores data as long as power is on. a) High complexity
b) High resolution
5. RAM is also known as __________
c) High speed main memory
a) RWM
d) High flexibility
b) MBR
c) MAR Answer: c
d) ROM Explanation: RAM is a volatile memory, therefore it
stores data as long as power is on. RAM is also known
as RWM (i.e. Read Write Memory). Computers a) Semiconductor RAMs are highly flexible
invariably use RAM for their high high-speed main b) Semiconductor RAMs have highest storing capacity
memory and then use backup or slower-speed c) Semiconductor RAMs are smaller in size
memories to hold auxiliary data. d) All of the Mentioned
10. How many types of RAMs are? Answer: d

a) 2 Explanation: RAM is a volatile memory, therefore it
b) 3 stores data as long as power is on. RAM is also known
c) 4 as RWM (i.e. Read Write Memory). The magnetic core
d) 5 memories have been replaced by semiconductor
RAMs because of smaller in size, high storing capacity
Answer: a as well as flexibility.
Explanation: There are two types of RAM and these
are static and dynamic. Static RAM(SRAM) is faster 15. The data written in flip-flop remains stored as long
than dynamic RAM(DRAM) as the access time for as __________
DRAM is more compared to that of SRAM. a) D.C. power is supplied
b) D.C. power is removed
11. Static RAM employs __________ c) A.C. power is supplied
a) BJT or MOSFET d) A.C. power is removed
b) FET or JFET
c) Capacitor or BJT Answer: a
d) BJT or MOS Explanation: Since flip-flops are made up of
semiconductor materials. So, it can’t accept A.C.
Answer: d source and the data written in flip-flop remains stored
Explanation: Static RAM employs bipolar or MOS as long as the dc power is maintained.
flip-flops because both the semiconductor has storing
capacity. Thus, it’s access time is less and it is faster in
operation. TOPIC 5.2 MEMORY DECODING
12. Dynamic RAM employs __________ 1. Memory is a/an ___________

a) Capacitor or MOSFET a) Device to collect data from other computer
b) FET or JFET b) Block of data to keep data separately
c) Capacitor or BJT c) Indispensable part of computer
d) BJT or MOS d) Device to connect through all over the world
Answer: a Answer: c
Explanation: Dynamic RAM employs a capacitor or Explanation: Memory is an indispensable unit of a
MOSFET. Thus, it’s access time is more and it is computer and microprocessor based systems which
slower in operation. stores permanent or temporary data.
13. Which one of the following is volatile in nature? 2. The instruction used in a program for executing
a) ROM them is stored in the __________
b) EROM a) CPU
c) PROM b) Control Unit
d) RAM c) Memory
d) Microprocessor
Answer: d
Explanation: RAM is a volatile memory, therefore it Answer: c
stores data as long as power is on. RAM is also known Explanation: All of the program and the instructions
as RWM (i.e. Read Write Memory). RAMs are volatile are stored in the memory. The processor fetches it as
because the stored data will be lost once the d.c. power and when required.
applied to the flip-flops is removed.
3. A flip flop stores __________
14. The magnetic core memories have been replaced a) 10 bit of information
by semiconductor RAMs, why? b) 1 bit of information

c) 2 bit of information conductivity lies between that of conductor and
d) 3-bit information insulator.
Answer: b 8. Which one of the following has capability to store

Explanation: A flip-flop has capability to store 1 bit data in extremely high densities?
of information. It can be used further after erasing a) Register
previous information. b) Capacitor
c) Semiconductor
4. A register is able to hold __________ d) Flip-Flop
a) Data
b) Word Answer: c
c) Nibble Explanation: Semiconductor has capability to store
d) Both data and word data in extremely high densities.
Answer: b 9. A large memory is compressed into a small one by

Explanation: Register is also a part of memory inside using __________
a computer. It stands there to hold a word. A word is a a) LSI semiconductor
group of 16-bits or 2-bytes. b) VLSI semiconductor
c) CDR semiconductor
5. A register file holds __________ d) SSI semiconductor
a) A large number of word of information
b) A small number of word of information Answer: b
c) A large number of programs Explanation: VLSI (Very Large Scale Integration)
d) A modest number of words of information semiconductor is used in modern computers to short
the size of memory.
Answer: d
Explanation: A register file is different from a simple 10. VLSI chip utilizes __________
register because of capability to hold a modest number a) NMOS
of words of information. A word is a group of 16-bits b) CMOS
or 2-bytes. c) BJT
6. The very first computer memory consisted of
__________ Answer: d
a) A small display Explanation: VLSI (Very Large Scale Integration) is a
b) A large memory storage equipment memory chip which is made up of NMOS, CMOS,
c) An automatic keyboard input BJT, and BiCMOS. It can include 10,000 to 100,000
d) An automatic mouse input gates per IC.
Answer: b 11. CD-ROM refers to __________

Explanation: The very first computer memory a) Floppy disk
consisted of a minute magnetic toroid, which required b) Compact Disk-Read Only Memory
large, bulky circuit boards stored in large cabinates. c) Compressed Disk-Read Only Memory
d) Compressed Disk- Random Access Memory
7. A minute magnetic toroid is also called as
__________ Answer: b
a) Large memory Explanation: CD-ROM refers to Compact Disk-Read
b) Small memory Only Memory.
c) Core memory
d) Both small and large memory 12. Data stored in an electronic memory cell can be
accessed at random and on demand using __________
Answer: c a) Memory addressing
Explanation: A minute magnetic toroid is also called b) Direct addressing
as core memory which is made up of a semiconductor. c) Indirect addressing
A semiconductor is a device whose electrical d) Control Unit

Answer: b b) Microwave router
Explanation: Direct addressing eliminates the need to c) Telephone switch
process a large stream of irrelevant data in order to the d) All of the mentioned
desired data word.
Answer: d
13. The full form of PLD is __________ Explanation: IP router, microwave router and
a) Programmable Large Device telephone switch can be used as an intermediate device
b) Programmable Long Device between communication of two entities.
c) Programmable Logic Device
d) Programmable Lengthy Device 3. Which has comparatively high frequency
component?
Answer: c a) Sine wave
Explanation: The full form of PLD is Programmable b) Cosine wave
Logic Device. c) Square wave
d) None of the mentioned
14. The evolution of PLD began with __________
a) EROM Answer: c
b) RAM Explanation: Square wave has comparatively high
c) PROM frequency component in them.
d) EEPROM
4. Which has continuous transmission?
Answer: a a) Asynchronous
Explanation: The evolution of PLD (Programmable b) Synchronous
Logic Device) began with Programmable Read Only c) Asynchronous & Synchronous
Memory (i.e. PROM). Here, the ROM can be d) None of the mentioned
externally programmed as per the user.
Answer: b
15. A ROM is defined as __________ Explanation: Synchronous has continuous
a) Read Out Memory transmission where as asynchronous have sporadic
b) Read Once Memory transmission.
c) Read Only Memory
d) Read One Memory 5. Which requires bit transitions?
a) Asynchronous
Answer: c b) Synchronous
Explanation: A ROM is defined as Read Only c) Asynchronous & Synchronous
Memory which can read the instruction stored in a d) None of the mentioned
computer.
Answer: b
Explanation: Synchronous transmission needs bit
TOPIC 5.3 ERROR DETECTION AND transition.
CORRECTION
6. In synchronous transmission, receiver must stay
1. In layering, n layers provide service to synchronous for
a) n layer a) 4 bits
b) n-1 layer b) 8 bits
c) n+1 layer c) 9 bits
d) none of the mentioned d) 16 bits
Answer: c Answer: c
Explanation: In layering n layer provides service to Explanation: In synchronous transmission, receiver
n+1 layer and use the service provided by n-1 layer. must stay synchronous for 9 bits.
2. Which can be used as an intermediate device in 7. How error detection and correction is done?
between transmitter entity and receiver entity? a) By passing it through equalizer
a) IP router b) By passing it through filter

c) By amplifying it 2. ROM has the capability to perform _____________
d) By adding redundancy bits a) Write operation only
b) Read operation only
Answer: d c) Both write and read operation
Explanation: Error can be detected and corrected by d) Erase operation
adding additional information that is by adding
redundancy bits. Answer: b
Explanation: ROM means “Read Only Memory”.
8. Which is more efficient? Hence, it has capability to perform read operation only.
a) Parity check No write or erase operation could be performed in the
b) Cyclic redundancy check ROM.
c) Parity & Cyclic redundancy check
d) None of the mentioned 3. Since, ROM has the capability to read the
information only then also it has been designed, why?
Answer: b a) For controlling purpose
Explanation: Cyclic redundancy check is more b) For loading purpose
efficient than parity check. c) For booting purpose
d) For erasing purpose
9. Which can detect two bit errors?
a) Parity check Answer: c
b) Cyclic redundancy check Explanation: ROM means “Read Only Memory”.
c) Parity & Cyclic redundancy check Hence, it has capability to perform read operation only.
d) None of the mentioned No write or erase operation could be performed in the
ROM. It has designed to provide the computer with
Answer: b resident programmes and for booting purpose.
Explanation: CRC is more powerful and it can detect
various kind of errors like 2 bit errors. 4. The ROM is a ___________
a) Sequential circuit
10. CRC uses b) Combinational circuit
a) Multiplication c) Magnetic circuit
b) Binary division d) Static circuit
c) Multiplication & Binary division
d) None of the mentioned Answer: b
Explanation: ROM is a combination of different ICs.
Answer: c So, it is a combinational circuit.
Explanation: CRC uses more math like multiplication It depends on present input and not past states.
and binary division.
5. ROM is made up of ___________
TOPIC 5.4 ROM a) NAND and OR gates
b) NOR and decoder
c) Decoder and OR gates
1. Which of the following has the capability to store d) NAND and decoder
the information permanently?
a) RAM Answer: c
b) ROM Explanation: ROM (Read Only Memory) has the
c) Storage cells capability to store the information permanently. ROM
d) Both RAM and ROM is made up of decoder and OR gates within a single IC
package.
Answer: b
Explanation: ROM (Read Only Memory) has the 6. Why are ROMs called non-volatile memory?
capability to store the information permanently. RAM a) They lose memory when power is removed
provides random access to memory. Storage cells are b) They do not lose memory when power is removed
responsible for the transfer of data from and into the c) They lose memory when power is supplied
memory. d) They do not lose memory when power is supplied

Answer: b 1. What is memory decoding?
Explanation: Volatile memory stores data as long as it a) The process of Memory IC used in a digital system
is powered. ROMs are called non-volatile memory is overloaded with data
because of they do not lose memory when power is b) The process of Memory IC used in a digital system
removed. is selected for the range of address assigned
c) The process of Memory IC used in a digital system
7. In ROM, each bit is a combination of the address is selected for the range of data assigned
variables is called ___________ d) The process of Memory IC used in a digital system
a) Memory unit is overloaded with data allocated in memory cell
b) Storage class
c) Data word Answer: b
d) Address Explanation: The Memory IC used in a digital system
is selected or enabled only for the range of addresses
Answer: d assigned to it and this process is called memory
Explanation: In ROM, each bit combination that decoding. It decodes the memory to be selected for a
comes out of the output lines is called data word. specific address.
Usually, a word consists of 16-bits or 2-bytes.
2. The first step in the design of memory decoder is
8. Which is not a removable drive? __________
a) Zip a) Selection of a EPROM
b) Hard disk b) Selection of a RAM
c) Super Disk c) Address assignment
d) Jaz d) Data insertion
Answer: c Answer: c
Explanation: Hard disk is present inside a computer. Explanation: Memory decoder decodes the memory to
So, it is not a removable drive. be selected for a specific address. The first step in the
design of memory decoder is address assignment in
9. In ROM, each bit combination that comes out of the non-overlapped manner.
output lines is called ___________
a) Memory unit 3. How many address bits are required to select
b) Storage class memory location in Memory decoder?
c) Data word a) 4 KB
d) Address b) 8 KB
c) 12 KB
Answer: c d) 16 KB
Explanation: In ROM, each bit combination that
comes out of the output lines is called data word. Answer: c
Usually, a word consists of 16-bits or 2-bytes. Explanation: Memory decoder decodes the memory to
be selected for a specific address. Since, the given
10. VLSI chip utilizes ___________ EPROM and RAM are of 4 KB (4 * 1024 = 4096)
a) NMOS capacity, it requires 12 address bit to select one of the
b) CMOS 4096 memory locations.
c) BJT
d) All of the Mentioned 4. How memory expansion is done?
a) By increasing the supply voltage of the Memory ICs
Answer: d b) By decreasing the supply voltage of the Memory
Explanation: Very Large Scale Integration (VLSI) ICs
(ranging from 10,000 to 100,000 gates per IC) is a c) By connecting Memory ICs together
memory chip which is made up of NMOS, CMOS, d) By separating Memory ICs
BJT, and BiCMOS.
Answer: c
TOPIC 5.5 PROGRAMMABLE LOGIC Explanation: Memory ICs can be connected together
to expand the number of memory words or the number
ARRAY of bits per word.
5. IC 4116 is organised as _________ Answer: c
a) 512 * 4 Explanation: The full form of PLD is Programmable
b) 16 * 1 Logic Devices. It is a collection of gates, flip-flops and
c) 32 * 4 registers on a single chip.
d) 64 * 2
10. PLD contains a large number of _________
Answer: c a) Flip-flops
Explanation: IC 4116 is organised as 16 * 1 K which b) Gates
has capability to store 16 KB. c) Registers
6. To construct 16K * 4-bit memory, how many 4116
ICs are required? Answer: d
a) 1 Explanation: Programmable Logic Devices is a
b) 2 collection of a large number of gates, flip-flops,
c) 3 registers that are interconnected on the chip. Thus, it is
d) 4 used for designing logic circuits.
Answer: d 11. Logic circuits can also be designed using

Explanation: Since, IC 4116 is organised as 16K * 1, _________
which can store about 16KB data. So, four ICs are a) RAM
required for 16K * 4 memory implementation. b) ROM
c) PLD
7. How many 1024 * 1 RAM chips are required to d) PLA
construct a 1024 * 8 memory system?
a) 4 Answer: c
b) 6 Explanation: Programmable Logic Devices is a
c) 8 collection of large number of gates, flip-flops, registers
d) 12 that are interconnected on the chip. Thus, it is used for
designing logic circuits.
Answer: c
Explanation: One 1024 * 1 RAM chips is of 1-bit. 12. In PLD, there are provisions to perform
SO, for construction of 1024 * 8 RAM chip of 8-bits, interconnections of the gates internally, because of
it will require 8 chips. _________
a) High reliability
8. How many 16K * 4 RAMs are required to achieve a b) High conductivity
memory with a capacity of 64K and a word length of 8 c) The desired logic implementation
bits? d) The desired output
a) 2
b) 4 Answer: c
c) 6 Explanation: Programmable Logic Devices is a
d) 8 collection of a large number of gates, flip-flops,
registers that are interconnected on the chip. In PLD,
Answer: d there are provisions to perform interconnections of the
Explanation: 16K * 4 = 64K RAM is of 64K. gates internally so that the desired logic can be
Therefore, for a word of length 8-bits, implemented.
64 * 8 = 512K RAM required. Thus, number of 16K *
4 RAMs = 512/64 = 8. 13. Why antifuses are implemented in a PLD?
a) To protect from high voltage
9. The full form of PLD is _________ b) To increase the memory
a) Programmable Load Devices c) To implement the programmes
b) Programmable Logic Data d) As a switching devices
c) Programmable Logic Devices
d) Programmable Loaded Devices Answer: c
Explanation: Programmable Logic Devices is a
collection of a large number of gates, flip-flops,

registers that are interconnected on the chip. Logic consisting of programmable AND gates and
Programming is accomplished by using antifuses in a fixed OR gates.
PLD and it is fabricated at the cross points of the gates.
3. Outputs of the AND gate in PLD is known as
14. How many types of PLD is? ____________
a) 2 a) Input lines
b) 3 b) Output lines
c) 4 c) Strobe lines
d) 5 d) Control lines
Answer: a Answer: b
Explanation: There are two types of PLD, viz., Explanation: Outputs of the AND gate in PLD is
devices with fixed architecture and devices with a known as output lines.
flexible architecture. The main categories of PLDs are
PROM, PAL and PLA. 4. PLA contains ____________
a) AND and OR arrays
15. PLA refers to _________ b) NAND and OR arrays
a) Programmable Loaded Array c) NOT and AND arrays
b) Programmable Array Logic d) NOR and OR arrays
c) Programmable Logic Array
d) Programmed Array Logic Answer: a
Explanation: Programmable Logic Array is a type of
Answer: c fixed architecture logic devices with programmable
Explanation: PLA refers to Programmable Logic AND gates followed by programmable OR gates. It is
Array. It is a type of PLD having programmable AND a kind of PLD.
and OR gates.
5. PLA is used to implement ____________
a) A complex sequential circuit
TOPIC 5.6 PROGRAMMABLE ARRAY b) A simple sequential circuit
LOGIC c) A complex combinational circuit
d) A simple combinational circuit
1. The inputs in the PLD is given through
____________ Answer: c
a) NAND gates Explanation: Since, PLA is the combination of
b) OR gates programmable AND and OR gates. So, it is used to
c) NOR gates implement complex combinational circuit.
d) AND gates
6. A PLA is similar to a ROM in concept except that
Answer: d ____________
Explanation: The inputs in the PLD is given through a) It hasn’t capability to read only
AND gate followed by inverting & non-inverting b) It hasn’t capability to read or write operation
buffer. PLDs are Programmable Logic Devices c) It doesn’t provide full decoding to the variables
consisting of logic gates, flip-flops and registers d) It hasn’t capability to write only
connected together on a single chip. Thus, it can be
categorised into PROM, PAL and PLA. Answer: c
Explanation: A PLA is similar to a ROM in concept
2. PAL refers to ____________ except that it doesn’t provide full decoding to the
a) Programmable Array Loaded variables and doesn’t generate all the minterms as in
b) Programmable Logic Array the ROM. Programmable Logic Array is a type of
c) Programmable Array Logic fixed architecture logic devices with programmable
d) Programmable AND Logic AND gates followed by programmable OR gates. It is
a kind of PLD.
Answer: c
Explanation: PAL refers to Programmable Array 7. For programmable logic functions, which type of
PLD should be used?

a) PLA 11. If a PAL has been programmed once
b) PAL ____________
c) CPLD a) Its logic capacity is lost
d) SLD b) Its outputs are only active HIGH
c) Its outputs are only active LOW
Answer: b d) It cannot be reprogrammed
Explanation: Since PAL consists of programmable
AND gates and fixed OR gates and also circuitry Answer: d
working is less. Explanation: PAL only has a programmable AND
plane and a fixed OR plane. Since, PAL is dynamic in
8. The complex programmable logic device contains nature. So, it can’t be reprogrammed.
several PLD blocks and __________
a) A language compiler 12. The FPGA refers to ____________
b) AND/OR arrays a) First programmable Gate Array
c) Global interconnection matrix b) Field Programmable Gate Array
d) Field-programmable switches c) First Program Gate Array
d) Field Program Gate Array
Answer: c
Explanation: The complex programmable logic Answer: b
device contains several PLD blocks and a global Explanation: The FPGA refers to Field Programmable
interconnection matrix by which it communicates Gate Array. Field-Programmable Gate Arrays
through several devices. It is also known as Field- (FPGAs) are reprogrammable silicon chips. In contrast
Programmable Gate Arrays (FPGAs). to processors that you find in your PC, programming
an FPGA rewires the chip itself to implement your
9. Which type of device FPGA are? functionality rather than run a software application.
a) SLD Thus, FPGAs are PLD devices.
b) SROM
c) EPROM 13. The full form of VLSI is ____________
d) PLD a) Very Long Single Integration
b) Very Least Scale Integration
Answer: d c) Very Large Scale Integration
Explanation: Field-Programmable Gate Arrays d) Very Long Scale Integration
(FPGAs) are reprogrammable silicon chips. In contrast
to processors that you find in your PC, programming Answer: c
an FPGA rewires the chip itself to implement your Explanation: The full form of VLSI is Very Large
functionality rather than run a software application. Scale Integration in which FPGA is implemented.
Thus, FPGAs are PLD devices.
14. In FPGA, vertical and horizontal directions are
10. The difference between a PAL & a PLA is separated by ____________
____________ a) A line
a) PALs and PLAs are the same thing b) A channel
b) The PLA has a programmable OR plane and a c) A strobe
programmable AND plane, while the PAL only has a d) A flip-flop
programmable AND plane
c) The PAL has a programmable OR plane and a Answer: b
programmable AND plane, while the PLA only has a Explanation: The FPGA refers to Field Programmable
programmable AND plane Gate Array. Field-Programmable Gate Arrays
d) The PAL has more possible product terms than the (FPGAs) are reprogrammable silicon chips. Vertical
PLA and horizontal directions is separated by a channel in
an FPGA which determines the location of the output.
Answer: b
Explanation: The main difference between a PAL & 15. Applications of PLAs are _____________
PLA is that PLA has a programmable OR plane and a a) Registered PALs
programmable AND plane, while the PAL only has a b) Configurable PALs
programmable AND plane and a fixed OR plane.
c) PAL programming Answer: a
d) All of the Mentioned Explanation: Programmable Logic Array is a type of
fixed architecture logic devices with programmable
Answer: d AND gates followed by programmable OR gates. It is
Explanation: Applications of PLAs are as mentioned a kind of PLD.
above and these are performed by using an extra flip-
flop with PAL. 5. PLA is used to implement ____________
a) A complex sequential circuit
b) A simple sequential circuit
TOPIC 5.7 SEQUENTIAL c) A complex combinational circuit
PROGRAMMABLE DEVICES d) A simple combinational circuit
1. The inputs in the PLD is given through Answer: c

____________ Explanation: Since, PLA is the combination of
a) NAND gates programmable AND and OR gates. So, it is used to
b) OR gates implement complex combinational circuit.
c) NOR gates
d) AND gates 6. A PLA is similar to a ROM in concept except that
____________
Answer: d a) It hasn’t capability to read only
Explanation: The inputs in the PLD is given through b) It hasn’t capability to read or write operation
AND gate followed by inverting & non-inverting c) It doesn’t provide full decoding to the variables
buffer. PLDs are Programmable Logic Devices d) It hasn’t capability to write only
consisting of logic gates, flip-flops and registers
connected together on a single chip. Thus, it can be Answer: c
categorised into PROM, PAL and PLA. Explanation: A PLA is similar to a ROM in concept
except that it doesn’t provide full decoding to the
2. PAL refers to ____________ variables and doesn’t generate all the minterms as in
a) Programmable Array Loaded the ROM. Programmable Logic Array is a type of
b) Programmable Logic Array fixed architecture logic devices with programmable
c) Programmable Array Logic AND gates followed by programmable OR gates. It is
d) Programmable AND Logic a kind of PLD.
Answer: c 7. For programmable logic functions, which type of

Explanation: PAL refers to Programmable Array PLD should be used?
Logic consisting of programmable AND gates and a) PLA
fixed OR gates. b) PAL
c) CPLD
3. Outputs of the AND gate in PLD is known as d) SLD
____________
a) Input lines Answer: b
b) Output lines Explanation: Since PAL consists of programmable
c) Strobe lines AND gates and fixed OR gates and also circuitry
d) Control lines working is less.
Answer: b 8. The complex programmable logic device contains

Explanation: Outputs of the AND gate in PLD is several PLD blocks and __________
known as output lines. a) A language compiler
b) AND/OR arrays
4. PLA contains ____________ c) Global interconnection matrix
a) AND and OR arrays d) Field-programmable switches
b) NAND and OR arrays
c) NOT and AND arrays Answer: c
d) NOR and OR arrays Explanation: The complex programmable logic
device contains several PLD blocks and a global

interconnection matrix by which it communicates 12. The FPGA refers to ____________
through several devices. It is also known as Field- a) First programmable Gate Array
Programmable Gate Arrays (FPGAs). b) Field Programmable Gate Array
c) First Program Gate Array
9. Which type of device FPGA are? d) Field Program Gate Array
a) SLD
b) SROM Answer: b
c) EPROM Explanation: The FPGA refers to Field Programmable
d) PLD Gate Array. Field-Programmable Gate Arrays
(FPGAs) are reprogrammable silicon chips. In contrast
Answer: d to processors that you find in your PC, programming
Explanation: Field-Programmable Gate Arrays an FPGA rewires the chip itself to implement your
(FPGAs) are reprogrammable silicon chips. In contrast functionality rather than run a software application.
to processors that you find in your PC, programming Thus, FPGAs are PLD devices.
an FPGA rewires the chip itself to implement your
functionality rather than run a software application. 13. The full form of VLSI is ____________
Thus, FPGAs are PLD devices. a) Very Long Single Integration
b) Very Least Scale Integration
10. The difference between a PAL & a PLA is c) Very Large Scale Integration
____________ d) Very Long Scale Integration
a) PALs and PLAs are the same thing
b) The PLA has a programmable OR plane and a Answer: c
programmable AND plane, while the PAL only has a Explanation: The full form of VLSI is Very Large
programmable AND plane Scale Integration in which FPGA is implemented.
c) The PAL has a programmable OR plane and a
programmable AND plane, while the PLA only has a 14. In FPGA, vertical and horizontal directions are
programmable AND plane separated by ____________
d) The PAL has more possible product terms than the a) A line
PLA b) A channel
c) A strobe
Answer: b d) A flip-flop
Explanation: The main difference between a PAL &
PLA is that PLA has a programmable OR plane and a Answer: b
programmable AND plane, while the PAL only has a Explanation: The FPGA refers to Field Programmable
programmable AND plane and a fixed OR plane. Gate Array. Field-Programmable Gate Arrays
(FPGAs) are reprogrammable silicon chips. Vertical
11. If a PAL has been programmed once and horizontal directions is separated by a channel in
____________ an FPGA which determines the location of the output.
a) Its logic capacity is lost
b) Its outputs are only active HIGH 15. Applications of PLAs are _____________
c) Its outputs are only active LOW a) Registered PALs
d) It cannot be reprogrammed b) Configurable PALs
c) PAL programming
Answer: d d) All of the Mentioned
Explanation: PAL only has a programmable AND
plane and a fixed OR plane. Since, PAL is dynamic in Answer: d
nature. So, it can’t be reprogrammed. Explanation: Applications of PLAs are as mentioned
above and these are performed by using an extra flip-
flop with PAL.

CS8351 Digital Principles and System Design MCQ

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CS8351 Digital Principles and System Design MCQ

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CS8351 DPSD CSE - Regulations 2017

CSE - 5th Semester remainders.

4. The representation of octal number (532.2)8 in

Answer: c 6. An important drawback of binary system is

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Answer: b The gate is either _________

13. In case of XOR/XNOR simplification we have to Answer: d

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UNIT II COMBINATIONAL 2. Which of the following logic expressions represents

1. Which of the circuits in figure (a to d) is the sum-of-

3. The device shown here is most likely a ________

4. What type of logic circuit is represented by the

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8. For the device shown here, assume the D input is

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5. Procedure for the design of combinational circuits

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Answer: b 4. If we record any music in any recorder, such types

1. How many inputs will a decimal-to-BCD encoder Answer: b

10. Can an encoder be called as multiplexer?

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9. If the number of n selected input lines is equal to

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Answer: c 5. The use of VHDL can be done in _____ ways.

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L1: ARCHITECTURE mux1 OF mux IS d)

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UNIT III SYNCHRONOUS

Answer: a 1. Latches constructed with NOR and NAND gates

9. A 4 to 16 decoder can be used as a code converter. Answer: d

Answer: c 8. Whose operations are more faster among the

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6. The full form of SR is ___________

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7. Synchronous counter is a type of ____________ Answer: a

6. A user has designed JK flip flop by using the VHDL

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5. Which is the delay elements for clocked system?

Answer: b TOPIC 4.2 HAZARDS

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7. The pipeline bubbling is a method used to prevent UNIT V MEMORY AND

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10. How many types of RAMs are? Answer: d

12. Dynamic RAM employs 1. Memory is a/an _