TH8056

Enhanced Single Wire CAN Transceiver

Features
‰ Fully compliant to GMW3089 V2.4 and J2411 Single Wire CAN specification for Class B
in-vehicle communications
‰ Only 60 µA worst case sleep mode current independent from CAN voltage range
‰ Operating voltage range 5V to 26.5V
‰ Up to 40 kbps bus speed
‰ Up to 100 kbps high-speed transmission mode
‰ Logic inputs compatible with 3.3V and 5V supply systems
‰ Control pin for external voltage regulators
‰ Low RFI due to output wave shaping in normal and high voltage wake up mode
‰ Fully integrated receiver filter
‰ Bus terminals proof against short-circuits and transients in automotive environment
‰ Loss of ground protection, very low leakage current (typ. 20µA at 26.5V and 125°C)
‰ Protection against load dump, jump start
‰ Thermal overload and short circuit protection
‰ Under voltage lockout
‰ Bus dominant time-out feature
‰ Pb-Free 14-pin thermally enhanced and 8-pin SOIC package

Ordering Information
Part No. Temperature Range Package Revision

TH8056 KDC A -40 to 125 °C SOIC14 A

TH8056 KDC A8 -40 to 125 °C SOIC8 A

General Description
The TH8056 is a physical layer device for a single wire data link capable of operating with various CSMA/CR protocols
such as the Bosch Controller Area Network (CAN) version 2.0. This serial data link network is intended for use in
applications where a high data rate is not required and a lower data rate can achieve cost reductions in both the physical
media components and the microprocessor and/or dedicated logic devices that use the network.

The network shall be able to operate in either the normal data rate mode or the high-speed data download mode for
assembly line and service data transfer operations. The high-speed mode is only intended to be operational when the
bus is attached to an off-board service node. This node shall provide temporary bus electrical loads which facilitate
higher speed operation.

The bit rate for normal communications is typically 33.33kbit/s, for high-speed transmissions as described above a typical
bit rate of 83.33kbit/s is recommended. The TH8056 is designed in accordance with the Single Wire CAN Physical Layer
Specification GMW3089 V2.4 and supports many additional features like under-voltage lock-out, time-out for faulty
blocked input signals, output blanking time in case of bus ringing and a very low sleep mode current.

TH8056 – Datasheet Page 1 of 26 March 2007

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Contents
1. Functional Diagram ....................................................................................................3

2. Electrical Specification ..............................................................................................4

2.1 Operating Conditions.............................................................................................4
2.2 Absolute Maximum Ratings ...................................................................................4
2.3 Static Characteristics.............................................................................................5
2.4 Dynamic Characteristics........................................................................................7
2.5 Bus loading requirements......................................................................................8
2.6 Timing Diagrams ...................................................................................................9

3. Functional Description.............................................................................................11
3.1 TxD Input pin .......................................................................................................11
3.2 Mode 0 and Mode 1 pins .....................................................................................11
3.3 RxD Output pin ....................................................................................................12
3.4 Bus LOAD pin......................................................................................................12
3.5 Vbat INPUT pin....................................................................................................13
3.6 CAN BUS pin.......................................................................................................13
3.7 INH Pin (TH8056 KDC A8 only)...........................................................................13
3.8 State Diagram......................................................................................................14
3.9 Power Dissipation................................................................................................15
3.10 Application Circuitry.............................................................................................17

4. Pin Description .........................................................................................................18

5. Package Dimensions................................................................................................19
5.1 SOIC14................................................................................................................19
5.2 SOIC8..................................................................................................................20

6. Tape and Reel Specification ....................................................................................21

6.1 Tape Specification ...............................................................................................21
6.2 Reel Specification for SOIC14NB ........................................................................22

7. ESD/EMC Remarks ...................................................................................................23

7.1 General Remarks ................................................................................................23
7.2 ESD-Test .............................................................................................................23
7.3 EMC ....................................................................................................................23
7.4 Latch Up Test ......................................................................................................23

8. Revision History .......................................................................................................24

9. Assembly Information ..............................................................................................25

10. Disclaimer..............................................................................................................26

TH8056 – Datasheet Page 2 of 26 March 2007

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1. Functional Diagram

VBAT INH *

TH8056

5V Supply & Biasing&

References VBAT Monitor
Reverse
Current
Protection
RCOsc

Wave Shaping
CAN Driver CANH
TxD Time Out

Feedback-
Loop

Input
Filter

MODE0
MODE
CONTROL LOAD
MODE1 Loss of
Receive
Ground
Comparator
Detection

Reverse
Current
Protection
Wake up filter

RxD

RxD Blanking
Time Filter
GND

Figure 1 - Block Diagram

* INH terminal is present on TH8056 KDC A only

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2. Electrical Specification
All voltages are referenced to ground (GND). Positive currents flow into the IC.
The absolute maximum ratings (in accordance with IEC 134) given in the table below are limiting values that
do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term
exposure to limiting values may affect the reliability of the device.

2.1 Operating Conditions

Parameter Symbol Min Max Unit

Battery voltage VBAT 5.0 18 V

Operating ambient temperature for TH8056 KDC A TA -40 125 °C
Junction temperature TJ -40 150 °C

2.2 Absolute Maximum Ratings

Parameter Symbol Condition Min Max Unit
Supply Voltage VBAT -0.3 18 V
Load dump; t<500ms 40
Short-term supply voltage VBAT.ld V
Jump start; t<1min 26.5
Transient supply voltage VBAT.tr1 ISO 7637/1 pulse 1[1] -50 V
Transient supply voltage VBAT..tr2 ISO 7637/1 pulses 2[1] 100 V
Transient supply voltage VBAT..tr3 ISO 7637/1 pulses 3A, 3B -200 200 V
VBAT <= 26.5V -20 40
CANH voltage VCANH V
VBAT = 0 -40 40
Transient bus voltage VCANH..tr1 ISO 7637/1 pulse 1 [2] -50 V
Transient bus voltage VCANH.tr2 ISO 7637/1 pulses 2 [2] 100 V
Transient bus voltage VCANH.tr3 ISO 7637/1 pulses 3A, 3B [2] -200 200 V
DC voltage on pin LOAD VLOAD via RT > 2kΩ -40 40 V
DC voltage on pins TxD, MODE1, MODE0,RxD, VDC -0.3 7 V
Human body model,
ESD capability of any pin (Human Body Model) ESDHBM equivalent to discharge -2 2 kV
100pF with 1.5kΩ,
Maximum latch – up free current at any Pin ILATCH -500 500 mA
in free air, SOIC14 70
Thermal impedance [3] ΘJA K/W
in free air, SOIC8 150
Storage temperature Tstg -55 150 °C
Junction temperature Tvj -40 150 °C

[1]
ISO 7637 test pulses are applied to VBAT via a reverse polarity diode and >1uF blocking capacitor .
[2]
ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1 nF.
[3]
The application board shall be realized with a ground copper foil area >150mm2 (low conductance board in accordance to
JEDEC51-7)

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2.3 Static Characteristics

Unless otherwise specified all values in the following tables are valid for VBAT = 5V to 26.5V and TAMB=-40°C
to 125oC. All voltages are referenced to ground (GND), positive currents flow into the IC.

Parameter Symbol Condition Min Typ Max Unit

PIN VBAT
Operating supply voltage VBAT 6 12 18 V
Low battery operating supply voltage VBAT_L except high-speed/sleep mode 5 6 V
T<1min, Tamb < 85°C
Short duration Operating supply voltage VBAT_JS 18 26.5 V
(except high-speed mode)
Under-voltage lock-out VBATuv 4.0 4.8 V
Supply current, recessive, all active modes IBAT VBAT = 18V , TxD open 5 8 mA
VBAT = 26.5V
Normal mode supply current, dominant IBATN [2] MODE0=MODE1=H TxD=L, 30 35 mA
Rload = 200Ω
VBAT = 16V
High-speed mode supply current, dominant IBATH [2] MODE0=H,MODE1=L,TxD=L, 60 75 mA
Rload = 75Ω
VBAT = 26.5V
Wake-up mode supply current, dominant IBATW [2] MODE0=L,MODE1=H, TxD=L, 60 75 mA
Rload = 200Ω
Sleep mode supply current IBATS VBAT =13V, Tamb < 85°C 40 60 µA
PIN CANH
RL > 200Ω,
Bus output voltage, low battery Voh_l Normal, high-speed mode, 3.4 5.1 V
5V < VBAT < 6V
RL > 200Ω, Normal mode,
Bus output voltage Voh 4.4 5.1 V
6V < VBAT < 26.5V
RL > 75Ω, high-speed mode,
Bus output voltage, high-speed mode Voh 4.2 5.1 V
8V < VBAT < 16V
Wake-up mode, RL > 200Ω,
Fixed Wake-up Output High Voltage VohWuFix 9.9 12.5 V
11.2V < VBAT < 26.5V
Wake-up mode, RL > 200Ω,
Offset Wake-up Output High Voltage VohWuOffset VBAT – 1.5 VBAT V
5V < VBAT < 11.2V
Recessive state or sleep mode,
Recessive state output voltage Vol -0.2 0.20 V
Rload = 6.5 kΩ,
VCANH = 0V, VBAT = 26.5V,
Bus short circuit current -ICAN_SHORT 50 350 mA
TxD = 0V
Bus leakage current during loss of ground ILKN_CAN[1] Loss of ground, VCANH = 0V -50 10 µA
Bus leakage current, bus positive ILKP_CAN TxD high; -10 10 µA
Bus input threshold Vih Normal, high-speed mode 2.0 2.1 2.2 V
Bus input threshold low battery Vihlb Normal mode 5V<VBAT<6V 1.6 1.7 2.2 V
Fixed Wake-up Input High Voltage
VihWuFix[2] Sleep mode, VBAT > 11.2V 6.6 7.9 V
Threshold
Offset Wake-up Input High Voltage
VihWuOffset[2] Sleep mode VBAT-4.3 VBAT-3.25 V
Threshold

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Parameter Symbol Condition Min Typ Max Unit

PIN LOAD
ILOAD = 1mA, all active modes
Voltage on switched ground pin VLOAD 0.1 V
and sleep mode
Voltage on switched ground pin VLOAD_LOB ILOAD = 7mA , VBAT = 0V 1 V
RLOAD RLOAD
Load resistance during loss of battery RLOAD_LOB VBAT = 0 Ω
-10% +35%
PIN TXD,MODE0,MODE1
High level input voltage Vih 2.0 V
Low level input voltage Vil 0.65 V
TxD pull-up current -IIL_TXD TxD = L, MODE0 and 1 = H 20 50 µA
MODE pull-down resistor RMODE_pd 20 50 kΩ
PIN RXD
Low level output voltage Vol_rxd IRxD = 2mA 0.4 V
High level output leakage Iih_rxd VRxD = 5V -10 10 µA
RxD output current Irxd VRxD = 5V 70 mA
PIN INH
High level output voltage Voh_INH IINH = -180µA VS -0.8V VS-0.5V V
Leakage current IINH_lk Mode0/1 = L ,VINH = 0V -5 5 µA
Over-temperature Protection
Thermal shutdown Tsd [2] 155 180 °C
Thermal recovery Trec [2] 126 150 °C

[1]
Leakage current in case of loss of ground is the sum of both currents ILKN_CAN and ILKN_LOAD .
[2]
Thresholds are not tested in production, but characterized and guaranteed by design

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2.4 Dynamic Characteristics

Unless otherwise specified all values in the following table are valid for VBAT = 5V to 26.5V and TAMB= -40°C
to 125oC.

Parameter Symbol Condition Min Typ Max Unit

Transmit delay in normal and wake-up min and max loads acc. To
tTr [1] 2 6.3 µs
mode, rising edge 2.5 Bus loading requirements

Transmit delay in wake-up mode to VihWU, min and max loads acc. To
tTWUr [2] 3 18 µs
rising edge 2.5 Bus loading requirements

Transmit delay in normal mode, min and max loads acc. To

tTf [3] 1.8 10 µs
falling edge 2.5 Bus loading requirements

Transmit delay in wake-up mode, min and max loads acc. To

tTWU1f [3] 3 13.7 µs
falling edge 2.5 Bus loading requirements

Transmit delay in high-speed mode, min and max loads acc. To

tTHSr [4] 0.1 1.5 µs
rising edge 2.5 Bus loading requirements

Transmit delay in high-speed mode, min and max loads acc. To

tTHSf[5] 0.04 3 µs
falling edge 2.5 Bus loading requirements

Receive delay , all active modes tDR [6] CANH high to low transition 0.2 1 µs

Receive delay , all active modes tRD [6] CANH low to high transition 0.2 1 µs

Input minimum pulse length, all active

tmpDR [6] CANH high to low transition 0.1 1 µs
modes

Input minimum pulse length, all active

tmpRD [6] CANH low to high transition 0.1 1 µs
modes

Wake-up filter time delay tWUF See diagrams, Figure 3 10 70 µs

Receive blanking time after

trb See diagrams, Figure 4 0.5 6 µs
TxD L-H transition

TxD time-out reaction time ttout All active modes 10 30 ms

Delay from Normal to High-speed/HVWU

tdnhs 30 ms
Mode

Delay from High-speed /HVWU to Normal

tdhsn 30 ms
Mode

Delay from Normal Mode to Standby tdsby VBAT = 6V to 26.5V 500 µs

Delay from Standby to Sleep Mode tdsleep VBAT = 6V to 26.5V 100 500 ms

Delay from Sleep to normal Mode tdsnwu VBAT = 6V to 26.5V 50 ms

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[1]
The maximum signal delay time for a bus rising edge is measured from Vcmos il on the TxD input pin to the VihMax + V g off max
level on CANH at maximum network time constant , minimum signal delay time for a bus rising edge is measured from Vcmos ih
on the TxD input pin to 1V on CANH at minimum network time constant .These definitions are valid in both normal and HVWU
mode
[2]
The maximum signal delay time for a bus rising edge in HVWU mode is measured from Vcmos il on the TxD input pin to the
VihWUMax + V g off max level on CANH at maximum network time constant, minimum signal delay time for a bus rising edge is
measured from Vcmos ih on the TxD input pin to 1V on CANH at minimum network time constant
[3]
Maximum signal delay time for a bus falling edge is measured from V cmos ih on the TxD input pin to 1V on CANH at maximum
network time constant, minimum signal delay time for a bus falling edge is measured from V cmos ih on the TxD input pin to the
VihMax + V g off max level on CANH. These definitions are valid in both normal and HVWU mode.
[4]
The signal delay time in high-speed mode for a bus rising edge is measured from Vcmos il on the TxD input pin to the VihMax + V g
max level on CANH at maximum high-speed network time constant.
off
[5]
The signal delay time in high-speed mode for a bus falling edge is measured from Vcmos ih on the TxD input pin to 1V on CANH
at maximum high-speed network time constant
[6]
Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling
(Vcmos_il_max) / rising (Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH.
The minimum slew rate for the bus rising and falling edges is 50V/us. The low level on bus is always 0V. For normal mode
and high-speed mode testing the high level on bus is 4V. For HVWU mode testing the high level on bus is Vbat – 2V.

2.5 Bus loading requirements

Parameter Symbol Min Typ Max Unit

Number of system nodes 2 32

Network distance between any two ECU nodes Bus length 60 M

Node Series Inductor Resistance (if required) Rind 3.5 Ohm

Ground Offset Voltage Vgoff 1.3 V

Ground Offset Voltage, low battery Vgofflb 0.1 VBAT 0.6 V

Device Capacitance (unit load) Cul 135 150 300 pF

Network Total Capacitance Ctl 396 19000 pF

Device Resistance (unit load) Rul 6435 6490 6665 Ohm

Device Resistance (min load) Rmin 2000 Ohm

Network Total Resistance Rtl 200 3332 Ohm

High-Speed Mode Network Resistance to GND Rload 75 135 Ohm

Network Time Constant [1] τ 1 4 µs

Network Time Constant, high-speed mode [1] τ 1.5 µs

[1]
The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emissions. The
maximum value is selected to ensure proper communication under all communication modes. Not all combinations of R and C are
possible. The following load conditions are used for the measurement of the dynamic characteristics:

Normal and high volt. Wake-up mode High-speed mode

min.load/min tau 3.3KΩ/ 540pF Additional 140Ω tool resistance to
min.load/max tau 3.3KΩ/ 1.2nF ground in parallel
max.load/min tau 200Ω/ 5nF Additional 120Ω tool resistance to
max.load/max tau 200Ω/ 20nF ground in parallel

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2.6 Timing Diagrams

VTxD

50%

t
tT

VCANH

Vih max + Vgoff max

1V

tR tF
tD tDR

VRxD

50%

Figure 2 – Input / Output Timing

TH8056 – Datasheet Page 9 of 26 March 2007

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VCANH

Vih+Vgoff

tWU tWu

tWuF
VRxD
wake up
tWU < tWuF
interrupt
t

Figure 3 – Wake-up Filter Time Delay

VTxD

50%

VCANH

Vih

VRxD

50%

trb

Figure 4 – Receive Blanking Time

TH8056 – Datasheet Page 10 of 26 March 2007

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3. Functional Description

3.1 TxD Input pin

Logic command to transmit on the single wire CAN bus

TxD Polarity
ƒ TxD = logic 1 (or floating) on this pin produces an undriven or recessive bus state (low bus voltage)
ƒ TxD = logic 0 on this pin produces either a bus normal or a bus high-voltage dominant state
depending on the transceiver mode state (high bus voltage)

If the TxD pin is driven to a logic low state while Mode 0,1 pins are in the 0,0 or sleep state, the transceiver
cannot drive the CAN Bus pin to the dominant state.
The transceiver provides an internal pull up on the TxD pin, which will cause the transmitter to default to the
bus recessive state, when TxD is not driven.
TxD input signals are standard CMOS logic levels for 3.3V and 5V supply voltages.

Time-out feature
In case of a faulty blocked dominant TxD input signal the CANH output is switched off automatically after the
specified TxD time-out reaction time to prevent a dominant bus. The transmission is continued by next TxD L
to H transition without delay.

3.2 Mode 0 and Mode 1 pins

Select transceiver operating modes

The transceiver provides a weak internal pull-down current on each of these pins, which causes the
transceiver to default to sleep mode when they are not driven. The Mode input signals are standard CMOS
logic level for 3.3V and 5V supply voltages.

M0 M1 Mode
L L Sleep Mode
H L High-Speed
L H High-Voltage Wake-Up
H H Normal Mode

Figure 5 – Truth Table

Mode 0 = 0, Mode 1 = 0 – Sleep mode

Transceiver is in low-power state, waiting for wake-up via high-voltage signal or by mode pins change to any
state other than 0,0. In this state, the CAN Bus pin is not in the dominant state regardless of the state of the
TxD pin.

Mode 0 = 1, Mode 1 = 0 – High-Speed mode

This mode allows high-speed download with bitrates up to 100Kbit/s. The output waveshaping circuit is
disabled in this mode. Bus transmitters which require communicating in high-speed mode are able to drive
reduced bus resistance during this mode.

Note: High-speed mode is only allowed with connected tool resistance in parallel to the network load. Otherwise the stability of the
output signal is not guaranteed because of the slew rate enhancement for the required rise times .

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Mode 0 = 0, Mode 1 = 1 – Transmit with high voltage signals to wake up remote nodes (HVWU)
This bus includes a selective node awake capability, which allows normal communication to take place
among some nodes while leaving the other nodes in an undisturbed sleep state. This is accomplished by
controlling the signal voltages such that all nodes must wake up when they receive a higher voltage
message signal waveform. The communication system communicates to the nodes information as to which
nodes are to stay operational (awake) and which nodes are to put themselves into a non-communicating
low-power “sleep” state. Communication at the lower, normal voltage levels does not disturb the sleeping
nodes.

Mode 0 = 1, Mode 1 = 1 – Normal speed and signal voltage mode

Transmission bit rate in normal communication is 33.333 Kbits/sec. In normal transmission mode the
TH8056 supports controlled waveform rise and overshoot times. Waveform trailing edge control is required
to assure that high frequency components are minimized at the beginning of the downward voltage slope.
The remaining fall time occurs after the bus is inactive with drivers off and is determined by the RC time
constant of the total bus load.

3.3 RxD Output pin

Logic data as sensed on the single wire CAN bus

RxD polarity
RxD = logic 1 on this pin indicates a bus recessive state (low bus voltage)
RxD = logic 0 on this pin indicates a bus normal or high-voltage bus dominant state

RxD in Sleep Mode

RxD does not pass signals to the micro processor while in sleep mode until a valid wake-up bus voltage level
is received or the Mode 0, 1 pins are not 0,0 respectively. When the valid wake-up bus signal awakens the
transceiver, the RxD pin signalizes an interrupt (logic 0 for dominant high-voltage signal). If there is no mode
change within the time stated, the transceiver reenters the sleep mode as described in 3.7

When not in sleep mode all valid bus signals will be sent out on the RxD pin.

RxD Typical Load

Resistance: 2.7 kohms
Capacitance: < 25 pF

3.4 Bus LOAD pin

Resistor ground with internal open-on-loss-of-ground protection

When the ECU experiences a loss of ground condition, this pin is switched to a high impedance state.

The ground connection through this pin is not interrupted in any transceiver operating mode including the
sleep mode. The ground connection is interrupted only when there is a valid loss of ground condition.

This pin provides the bus load resistor with a path to ground which contributes less than 0.1 volts to the bus
offset voltage when sinking the maximum current through one unit load resistor.

The transceiver’s maximum bus leakage current contribution to Vol from the LOAD pin when in a loss of
ground state is 50 uA over all operating temperatures and 3.5 V < Vbatt < 26.5V.

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3.5 Vbat INPUT pin

Vehicle Battery Voltage

The transceiver is fully operational as described in chapter 2 over the range 6V<Vbat IC<18V as measured
between the GND pin and this pin.
For 5V < Vbat IC < 6V the bus operates in normal mode with reduced dominant output voltage and reduced
receiver input voltage. High voltage wake-up call is not possible (dominant output voltage is the same as in
normal or high-speed mode).
The transceiver operates in normal mode and high-voltage wake-up mode if 18V < Vbat IC < 26.5V at 85°C for
one minute.

For 0V< Vbat IC < 4.8V, the bus is passive (not driven dominantly) and RxD is undriven (high), regardless of
the state of the TxD pin (under-voltage lock-out).

3.6 CAN BUS pin

Bus Input/Output

Wave Shaping in normal and HVWU mode

Wave shaping is incorporated into the transmitter to minimize EMI radiated emissions. An important
contributor to emissions is the rise and fall times during output transitions at the “corners” of the voltage
waveform. The resultant waveform is one half of a sine wave of frequency 50 – 65 kHz at the rising
waveform edge and one quarter of this sine wave at falling or trailing edge.

Short circuits
If the CAN BUS pin is shorted to ground for any duration of time, the current is limited to the specified value,
until an over-temperature shut-down circuit disables the output high side drive source transistor (before the
local die temperature exceeds the damage limit threshold).

Loss of ground
In case of an ECU loss of ground condition, the LOAD pin is switched into high impedance state. The CANH
transmission is continued until the under-voltage lock-out voltage threshold is detected.

Loss of battery
In case of battery loss (VBAT = 0 or open) the transceiver does not disturb bus communication. The
maximum reverse current into power supply system doesn’t exceed 500µA.

3.7 INH Pin (TH8056 KDC A only)

This Pin is a high-voltage highside switch used to control the ECU’s regulated microcontroller voltage supply.
After power-on the transceiver automatically enters an intermediate standby mode, the INH output will
become HIGH (VBAT) and therefore the external voltage regulator will provide the Vcc supply for the ECU .
If there is no mode change within the time stated, the transceiver reenters the sleep mode and the INH
output goes to logic 0 (floating). When the transceiver has detected a valid wake-up condition (bus HVWU
traffic which exceeds the wake-up filter time delay) the INH output will become HIGH (VBAT) again and the
same procedure starts as described after power-on. In case of a mode change into any active mode the
sleep timer is stopped and INH keeps high (VBAT) level. If the transceiver enters the sleep mode (M0,1=0),
INH goes to logic 0 (floating) no sooner than 100ms when no wake-up signal is present.

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3.8 State Diagram

HVWU Mode
M0 M1 INH

low high VBAT

M0/1 =>High

High Speed Mode

M0 M1 INH
VBATon
high low VBAT

Normal Mode
M0&1=>Low
M0 M1 INH

high high VBAT

M0/1 =>High
(if VCC_ECU on)

VBAT standby
M0/1 INH RxD CAN
after min. 100ms
low VS high / float.
-> no mode change
low[1]
-> no valid wake up

wake up
request
from Bus
Sleep Mode

M0/1 INH/CAN

low floating

[1]
low after HVWU, high after VBAT on & VCCECU present

Figure 6 – State Diagram

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3.9 Power Dissipation

The TH8056 has an integrated protection against thermal overload. If the junction temperature reaches the
thermal shutdown threshold the TH8056 disables the transmitter driver to reduce the power dissipation to
protect the IC itself from thermal overload. The function of the transceiver will become again available if the
junction temperate drops below the thermal recovery temperature.

To secure a stable functioning within the application and to avoid a transmitter switch off due to thermal
overload under normal operating conditions, the application must take care of the maximum power
dissipation of the IC. The junction temperature can be calculated with:

TJ = Ta + Pd * θja
TJ Junction temperature
Ta Ambient temperature
Pd Dissipated power
θja Thermal resistance

The Junction temperature shouldn’t exceed under normal operating conditions the limit specified in chapter
2.3 Static Characteristics.

The power dissipation of an IC is the major factor determining the junction temperature. The TH8056
consumes current in different functions. A part of the supply current goes to the load and the other part
dissipates internally. The internal part has a constant passive part and an active part which depends on the
actual bus transmission. The complete internal part causes and increasing of the junction temperature.

Ptot = PINT_a + PINT_P

PINT_a Internal power dissipation active
PINT_p Internal power dissipation passive
Ptot Overall power dissipation
D Duty cycle for data transmission

The internal passive part can be calculated with the operating voltage and the normal mode supply current
recessive. The active part can be calculated with the voltage drop of the driving transistor and the current of
the CAN bus. The active part generates only during data transmission power dissipation. Therefore the duty
cycle has to be taken into account.

PINT_p = VBAT * IBAT

PINT_a = (VBAT – VCANH) * Iload * D
VBAT Battery supply voltage
IBAT Normal mode supply current recessive
Iload Can network current
D Duty cycle for data transmission
VCANH Voltage at CANH pin

The power dissipation of the load can be calculated with the CANH voltage and the CAN bus current.

Pload = VCANH * Iload * D

where
Iload = VCANH / Rload_net
Pload Power dissipation of the load resistor
Iload Current of CAN network
VCANH Voltage at CANH pin
Rload_net Network total resistance

TH8056 – Datasheet Page 15 of 26 March 2007

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Assumptions:
VBAT = 26.5V
Rload = 6.49 kΩ
Network with 32 nodes
VCANH = 5.1V
IBAT = 6mA
D = 50%
Ta = 125°C
ΘJA = 70k/W (Thermally enhanced SOIC14 package)

Computations:
Rload_net = 6.49kΩ / 32nodes = 203Ω
Iload = 5.1V / 203Ω = 25mA
Pload = 5.1V * 25mA * 0.5 = 64mW
PINT_a = (26.5V – 5.1V) * 25mA * 0.5 = 267mW
PINT_P = 26.5V * 6mA = 159mW
Ptot = 267mW + 159mW = 426mW
Tj = 125°C + 426mW * 70k/W = 155°C

The above calculation shows that under worst case conditions (max. operating voltage, max bus load, max
ambient temperature) the TH8056 with the thermally enhanced SOIC14 package operates below the thermal
limit. A stable functioning is possible up to these limits.

3.9.1. Thermal behaviour of TH8056 with SOIC8 – TH8056 KDC A8

The thermal impedance of an SOIC8 package is about twice in comparison to the thermally enhanced
SOIC14 package. Therefore the maximum power dissipation within this package is only about the half.
The using of the SOIC8 version of TH8056 depends on the network architecture (number of nodes), the
max. ambient temperature and the needed functionality (using of INH pin).
The following diagram shows the relationship between junction temperature, ambient temperature and
number of nodes, which have to be taken into account for using the SOIC8 version.

UBAT = 26.5V; Ta = 125°C

160 UBAT = 18V; Ta = 125°C

150 UBAT = 26.5V; Ta = 105°C

140
UBAT = 18V; Ta = 105°C
Junction Temperature

130
Save Operating Area
120
SOIC8 Package

UBAT = 26.5V; Ta = 85°C

110

100

90

80
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

Number of Network Nodes

Figure 7 – Save operating area of SOIC8 package

TH8056 – Datasheet Page 16 of 26 March 2007

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3.10 Application Circuitry

[1] other loads

VBAT
VBAT_ECU

Voltage regulator

VBAT

+5V ECU connector to

Single Wire CAN Bus

100nF

2.7k
INH VBAT
100pF
9 10
5 47µH
RxD
CAN controller

12
CANH

TH8056 1k
3 100pF
MODE0 6.49k

4
MODE1 11
LOAD
ESD Protection -
2 TPSMA16A or
TxD 1,7,8,14 MMBZ27VCLT1 or
equivalent

GND

[1] recommended capacitance at VBAT_ECU > 1uF (immunity to ISO7637/1 test pulses)

Figure 8 – Application Circuitry TH8056 KDC A

[1] other loads

VBAT
VBAT_ECU

Voltage regulator

VBAT

+5V ECU connector to

Single Wire CAN Bus

100nF

2.7k
VBAT
100pF
5
4 47µH
RxD
CAN controller

7
CANH

TH8056 1k
2 100pF
MODE0 6.49k

3
MODE1 6
LOAD
ESD Protection -
1 TPSMA16A or
TxD 8 MMBZ27VCLT1 or
equivalent

GND

[1] recommended capacitance at VBAT_ECU > 1uF (immunity to ISO7637/1 test pulses)

Figure 9 – Application circuitry TH8056 KDC A8

TH8056 – Datasheet Page 17 of 26 March 2007

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4. Pin Description

TH8056 KDC A TH8056 KDC A8

GND 1 14 GND TxD 1 8 GND

TxD 2 13 N.C. MODE0 2 7 CANH

TH8056
MODE0 3 12 CANH MODE1 3 6 LOAD

MODE1 4 TH8056 11 LOAD RXD 4 5 VBAT

RXD 5 10 VBAT

N.C. 6 9 INH

GND 7 8 GND

Pin Pin
Name IO-Typ Description
TH8056 KDC A TH8056 KDC A8

1 - GND P Ground
2 1 TXD I Transmit data from MCU to CAN
3 2 MODE0 I Operating mode select input 0
4 3 MODE1 I Operating mode select input 1
5 4 RXD O Receive data from CAN to MCU
6 - N.C.
7 - GND P Ground
8 - GND P Ground
Control Pin for external voltage regulator (high voltage
9 - INH O
high side switch)
10 5 VBAT P Battery voltage
11 6 LOAD O Resistor load (loss of ground low side switch )

12 7 CANH I/O Single wire CAN bus pin

13 - N.C.

14 8 GND P Ground

TH8056 – Datasheet Page 18 of 26 March 2007

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5. Package Dimensions
5.1 SOIC14

Small Outline Integrated Circiut (SOIC), SOIC 14, 150 mil

A1 B C D E e H h L A α ZD A2
All Dimension in mm, coplanarity < 0.1 mm
min 0.10 0.36 0.19 8.56 3.81 5.80 0.25 0.41 1.52 0° 1.37
1.27 0.51
max 0.25 0.45 0.25 8.74 3.99 6.20 0.50 1.27 1.72 8° 1.57
All Dimension in inch, coplanarity < 0.004”
min 0.004 0.014 0.0075 0.337 0.160 0.228 0.010 0.016 0.060 0° 0.054
0.050 0.020
max 0.01 0.018 0.0098 0.344 0.167 0.244 0.020 0.050 0.068 8° 0.062

TH8056 – Datasheet Page 19 of 26 March 2007

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5.2 SOIC8

Small Outline Integrated Circiut (SOIC), SOIC 8, 150 mil

A1 B C D E e H h L A α ZD A2
All Dimension in mm, coplanarity < 0.1 mm
min 0.10 0.36 0.19 4.80 3.81 5.80 0.25 0.41 1.52 0° 1.37
1.27 0.53
max 0.25 0.46 0.25 4.98 3.99 6.20 0.50 1.27 1.72 8° 1.57
All Dimension in inch, coplanarity < 0.004”
min 0.004 0.014 0.0075 0.189 0.150 0.2284 0.0099 0.016 0.060 0° 0.054
0.050 0.021
max 0.0098 0.018 0.0098 0.196 0.157 0.244 0.0198 0.050 0.068 8° 0.062

TH8056 – Datasheet Page 20 of 26 March 2007

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6. Tape and Reel Specification

6.1 Tape Specification

max. 10°

max. 10°

n.
IC pocket mi
R

Top View Sectional View

T2 P0

D0 P2
T

E
G1
< A0 >
K0 F
B1 B0 W

S1
G2 P1 D1
T1
Cover Tape

Ab i k l i ht

Standard Reel with diameter of 13“

Package Parts per Reel Width Pitch
SOIC14 2500 16 mm 8 mm
SOIC8 2500 12 mm 8 mm

D0 E P0 P2 Tmax T1 max G1 min G2 min B1 max D1 min F P1 Rmin T2 max W

SOIC14
1.5 1.75 4.0 2.0 7.5 4 – 12 16.0
0.6 0.1 0.75 0.75 12.1 1.5 30 8.0
+0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.3
SOIC8
1.5 1.75 4.0 2.0 5.5 4 12.0
0.6 0.1 0.75 0.75 8.2 1.5 30 6.5
+0.1 ±0.1 ±0.1 ±0.1 ±0.05 ±0.1 ±0.3

A0, B0, K0 can be calculated with package specification.

Cover Tape width 13.3 mm.

TH8056 – Datasheet Page 21 of 26 March 2007

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6.2 Reel Specification for SOIC14NB

W2

W1

B*

D* C
A N

Amax B* C D*min
330 2.0 ±0.5 13.0 +0,5/-0,2 20.2

Width of half reel Nmin W1 W2 max

4 mm 100.0 4.4 7.1
8 mm 100.0 8.4 11.1

TH8056 – Datasheet Page 22 of 26 March 2007

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7. ESD/EMC Remarks
7.1 General Remarks
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.

7.2 ESD-Test
The TH8056 is tested according to MIL883D (human body model).

7.3 EMC
The test on EMC impacts is done according to ISO 7637-1 for power supply pins and ISO 7637-3 for data-
and signal pins.

Power Supply pin VBAT, CANH, LOAD:

Testpulse Condition Duration
1 t1 = 5 s / US = -100 V / tD = 2 ms 5000 pulses
2 t1 = 0.5 s / US = 100 V / tD = 0.05 ms 5000 pulses
US = -200 V/ US = 200 V
3a/b 1h
burst 100ns / 10 ms / 90 ms break
Ri = 0.5 Ω, tD = 400 ms
5 10 pulses every 1min
tr = 0.1 ms / UP+US = 40 V

7.4 Latch Up Test

The TH8056 is tested according to JESD78 (Class 2).

TH8056 – Datasheet Page 23 of 26 March 2007

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8. Revision History

Version Changes Remark Date

001 Initial Release Sep. 2002
001a - Added chapter revision history March
- Error corrected within Figure 1 - Block Diagram 2003
002 - Pinout corrected within Figure 8 – Application Circuitry 06/13/03
003 - compatibility to GMW3089 Version 2.2 09/18/03
- Static Characteristics modified according to GMW3089 V2.2
- Dynamic Characteristics modified according to GMW3089 V2.2
- Bus loading requirements modified according to GMW3089 V2.2
- High-speed Mode added remark
- VBAT input pin description changed
- Add Tape and Reel Specification
- Change of ESD/EMC Remarks
004 - Changed application circuitry according to GMW3089 Rev.2.2 12/01/03
005 - Change of chapter 9. Assembly Information 05/13/04
006 - Change of Order Code 06/14/04
007 - Update of chapter “Features” with compatibility to GMW3089 24/06/04
V2.3 and very low leakage current during loss of ground
- Update of chapter “Features” high voltage wake up mode
instead of high speed ..
- Change of “Static characteristics”
o Supply current dominant
o Transmit delay
- Change of “Dynamic characteristics”
o Input min pulse length
o Condition for mode change from normal to standby,
standby to sleep and sleep to normal
- Change of application circuitry acc. To GMW3089 V2.3 Spec.
008 - Change of “Static characteristics” 31/08/04
o Offset Wake-up Output High Voltage
o Mode pull down resistor
009 - Additional Package Version SOIC8 15/04/05
- Additional chapter “Power Dissipation”
010 - Adaption of sleep mode condition acc. To GMW3089 Rev. 2.4 21/03/06
- Change of ESD capability of CANH pin
- Update of Assembly information
011 - Change of Parameter “Input minumum pulse length at CANH” 08/12/06
- Change of “Short duration operating supply voltage”
- Change of “Receive Delay”
- Change of “Low level input voltage” at TxD, Mode 0,1
012 - Change of load pin definition to be compliant to GMW3089 2.4 07/03/07

TH8056 – Datasheet Page 24 of 26 March 2007

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9. Assembly Information
Standard information regarding manufacturability of Melexis products with different soldering
processes

Our products are classified and qualified regarding soldering technology, solderability and moisture
sensitivity level according to following test methods:

Reflow Soldering SMD’s (Surface Mount Devices)

• IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
• EIA/JEDEC JESD22-A113
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)

Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)

• EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
• EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices

Iron Soldering THD’s (Through Hole Devices)

• EN60749-15
Resistance to soldering temperature for through-hole mounted devices

Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)

• EIA/JEDEC JESD22-B102 and EN60749-21

Solderability

For all soldering technologies deviating from above mentioned standard conditions (regarding peak
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests
have to be agreed upon with Melexis.

The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.

Melexis is contributing to global environmental conservation by promoting lead free solutions. For more
information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of
the Use of Certain Hazardous Substances) please visit the quality page on our website:
https://www.melexis.com/quality_leadfree.asp

TH8056 – Datasheet Page 25 of 26 March 2007

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10. Disclaimer

Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the
information set forth herein or regarding the freedom of the described devices from patent infringement.
Melexis reserves the right to change specifications and prices at any time and without notice. Therefore,
prior to designing this product into a system, it is necessary to check with Melexis for current information.
This product is intended for use in normal commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional
processing by Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential
damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical
data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering
of technical or other services.
© 2002 Melexis NV. All rights reserved.

For the latest version of this document. Go to our website at

www.melexis.com
Or for additional information contact Melexis Direct:

Europe and Japan: All other locations:

Phone: +32 1367 0495 Phone: +1 603 223 2362
E-mail: [email protected] E-mail: [email protected]

ISO/TS16949 and ISO14001 Certified

TH8056 – Datasheet Page 26 of 26 March 2007

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