Design and Simulation of Phase-Shifted Full

Bridge Converter for Hybrid Energy Systems

Oladimeji Ibrahim, Member IEEE Nor Zaihar Yahaya, Member IEEE
Department of Electrical and Electronics Engineering Nordin Saad, Member IEEE
Universiti Teknologi PETRONAS, K.Y. Ahmed
32610 Bander Seri Iskander, Perak, Malaysia Universiti Teknologi PETRONAS
[email protected] 32610 Bandar Seri Iskandar, Perak, Malaysia
[email protected]
[email protected]
[email protected]

AbstractThis paper presents design and Simulink stored in leakage inductance to cause severe ringing with power
implementation of zero voltage switching (ZVS) phase-shifted full FET junction capacitance [3, 4] .
bridge dc-dc converter. The phase-shifted full bridge PWM dc-dc The deficiency with parasitic ringing effect, conduction
converter is widely used in high power, high voltage applications losses and high power switching losses are elimination by
due to the advantages of high power handling capability with low employing phase-shifted PWM control signal which allows
switching and conduction losses. The phase shift feature of the ZVS transition of FET devices during the turn on. The ZVS soft
control signal allows ZVS thereby eliminating the switching losses switching is achieve during the turn on transition via resonance
during FET device transition. It also minimize the parasitic effect between the FET device output capacitance and the leakage
and conduction losses at high frequency operation thereby
inductance of the isolated transformer. In phase-shift full bridge
increase system efficiency. A 3kW, 100 kHz high frequency phase-
shifted full bridge converter was design and simulated in
dc-dc converter, the switching operation allows the transformer
Matlab/Simulink to analyze the system performance prior to primary to be connected to source voltage or shorted ensuring
experimental implantation. The converter is intended for hybrid continuous current flow thereby eliminating the ringing effect
energy systems (HES) application in which a state space controller that could result from transformer leakage inductance. The
will be developed with wider dynamics to accommodate variable energy stored in leakage inductance of the transformer is used
input sources mostly from renewable energy resources like solar to discharge the energy stored on the FET device (MOSFETs)
and wind power. The converter simulation results shows that the junction capacitance to achieve zero voltage switching (ZVS)
system achieved greater than 90% efficiency at full load current. at turn on [3, 5].
The ZVS phase-shift full bridge converter Allows operation
Keywordsdc-dc converter; phase-shift PWM; full bridge of switching devices at reduced switching losses and stress
converter; zero voltage switching thereby improving energy conversion efficiency. It also allows
operation of converts at high frequency resulting in high power
I. INTRODUCTION density [6, 7]. This paper presents analysis on modes of
The quest for high power density called for high frequency operations of phase-shifted full bridge converter and steady
operation of power converters [1]. Generally the FET devices state design of 3kW converter. The full bridge converter is
which are like the backbone of power converter has non-linear intended for hybrid energy system (HES) as shown in Fig.1
characteristics with their parasitic parameters effect more with five input sources in which a state space controller will be
pronounce at high frequency thereby deteriorating the system developed with wider dynamics to accommodate variable input
smooth operation for high efficiency delivery . In high power sources most especially from renewable energy sources. The
application, the full bridge converter topology is most widely designed converter is implemented in Simulink for examining
used owning to its high power handling capacity because of the the open loop performance of the system in terms of operation
number of field effect transistor (FET) switch in the topology and efficiency delivery. The simulation results shows that the
[2]. The switching mode of the FET device in full bridge system achieved over 90% efficiency at full load capacity.
converter have direct impact on the system performance in
terms of smooth operation and system efficiency. The pulse
width modulation (PWM) control signal to the gate of the four II. OPERATION AND STEADY STATE ANALYSIS
switches in conventional full bridge converter operation turns The phase-shifted PWM full bridge converter is an isolated
the diagonal pair switches at a time with or without dead time. dc-dc converter haven two stages, the dc-ac H bridge converter
This approach is referred to as hard switching resulting in high with high frequency transformer and the ac-dc part. The
switching losses within the circuit module reducing system topology of the ZVS phase-shift full bridge PWM converter has
efficiency. In situation where there is dead time, all four four switching element like conventional full bridge converter
switches will be in off state for short period and the load current as shown in Fig.1 with switching control signal been the major
freewheels through the rectifier diodes making the energy difference. The leg with pair switches S1, S2 are turned on
complimentarily with 50% duty cycle minus short dead time

978-1-5090-0845-2/16/$31.00 2016 IEEE

and same for the second leg with pair switches S3, S4. The current I p reverse to positive direction and rise to reach
gating signal is shown in Fig. 2, where the control signal to reflected output inductor current ( nI Lo ) at mode t = t1 .
switch S3 and S4 is phase-shifted with respect to gating signal
to switch S1 and S2 to allow ZVS transition and also ensuring
S1 S3 d3
that the transformer primary is either connected to the input or d1
C1 C3
D1 D3

shorted.
Llk
Vin RL
Co

S2 d2 S4 d4
C2 C4
D2
D4

Fig. 3. Mode 1 ( t0 ~ t1 )
Mode 2 ( t1 ~ t2 ), power delivery mode
At time t = t1 , the transformer secondary voltage is equal to
nVin and rectifier diode D1 and D4 are forward biased and
conduct to transfer power from source to the load. The effective
phase shift duty cycle starts with mode t1 ~ t2 , the current
across output filter start to rise and the primary winding current
I p then equal to reflected output inductor current ( nI Lo ).
Lo

Fig. 1. HES with phase-shifted full bridge converter S1 S3 d3

d1 D1 D3
C1 C3

Llk
Vin RL
Co

S2 d2 S4 d4
C2 C4
D2 D4

Fig. 4. Mode 2 ( t1 ~ t2 )
Mode 3 ( t2 ~ t3 ), Switch S3 ZVS
At mode t = t2 , switch S4 is turned off and the primary
current charges the snubber capacitance C 4 of switch S4 and
discharges capacitance of switch S3. When the snubber
capacitance C3 is completely discharge from Vin to 0, the body
diode d3 start to conduct to achieve zero voltage switching
Fig. 2. PWM Phase-shift full bridge converter waveform condition for switch S3 thereby eliminating FET device
switching losses. At this mode the transformer secondary
The operating waveform of the gating control signal and voltage become zero and the rectifier diodes D1 , D4 carrying
steady state transformer primary and secondary waveform of current.
ZVS Phase-shifted full bridge converter is presented in Fig. 2. Lo
The wave form shows the different transition mode within the
S1 d3
power circuit for a complete switching period ( t0 ~ t10 ) and each d1
C1
S3
C3
D1 D3

of this mode are briefly explained as follows [8]. Llk

Vin RL
Co

Mode 1 ( t0 ~ t1 ), duty cycle loss

S2 d2 C2 S4 d4
At the time, t = t0 the switch S1 and S4 are in on state, the C4
D2
D4
switch S1 turned on with ZVS following end of mode t10 . The
transformer secondary voltage Vs remains zero until the primary
Fig. 5. Mode 3 ( t2 ~ t3 )
 Mode 4 ( t3 ~ t4 ), freewheeling mode Lo
S1 S3 d3
d1 D1
At mode t = t3 , switch S3 is turned on with ZVS and the C1 C3
D3

primary current I p freewheel though switch S1 and S3. The Llk

Vin RL
transformer secondary voltage Vs is zero and the output Co

inductor voltage is discharged by the load. d2

S2 C2 S4 d4
C4
Lo
D2 D4

S1 S3 d3
d1 D1 D2
C1 C3 Fig. 8. Mode 6 ( t5 ~ t6 )
Llk
Vin RL
Mode 7 ( t6 ~ t7 ), power delivery mode
Co
At time t = t6 , the transformer secondary voltage Vs equals
S2 d2 S4 d4
C2 C4
D3
nVin . The rectifier diode D2 and D3 are forward biased and
D4 conduct to transfer power to charge the output inductor. The
effective phase shift duty cycle starts again with the mode t6 .
Fig. 6. Mode 4 ( t3 ~ t4 )
The current across output inductor start to rise and the primary
Mode 5 ( t4 ~ t5 ), switch S2 ZVS winding current I p in negative direction equal to reflected
At time t = t4 , switch S1 is turned off and the transformer output inductor current nI Lo .
primary current charges the snubber capacitance C1 of switch Lo

S1 and discharge capacitance C 2 of switch S2. When the S1 d3

d1 S3 D1 D3
snubber capacitance C 2 is completely discharge from Vin to 0, C1 C3

the body diode d2 start to conduct to achieve zero voltage Llk

Vin RL
switching condition for switch S2. The transformer secondary Co

voltage remain zero at mode t4 ~ t5 . d2

S2 S4 d4
C2 C4
D2 D4
S1 S3 d3
d1 D1 D2
C1 C3

Llk
Fig. 9. Mode 7 ( t6 ~ t7 )
Vin RL
Co
Mode 8 ( t7 ~ t8 ), switch S4 ZVS
S2 d2 C2 S4 d4
C4
At mode t = t7 switch S3 is turned off and the primary
D3
D4 current charges the snubber capacitance C3 of switch S3 and
discharges capacitance C 4 of switch S4. When the snubber
Fig. 7. Mode 5 ( t4 ~ t5 ) capacitance C 4 is completely discharged from Vin to 0, its body
diode d 4 start to conduct to achieve zero voltage switching
Mode 6 ( t5 ~ t6 ), duty cycle loss condition for switch S4. At this mode the transformer secondary
At the mode t = t5 , the switch S2 is turned on with ZVS voltage become zero and the rectifier diodes carrying current.

following end of mode t4 . The transformer secondary voltage Lo

S1
Vs still remain zero until the primary current I p reverse it d1 C1 S3 d3
D1 D3
C3
direction (in negative direction) and start to rise to reach
Llk
reflected output inductor current nI Lo at period t = t6 . The Vin RL
Co
primary current will rise with a slop of Vin / Llk as the Vin
S2 d2 C2 S4 d4
discharges the leakage inductor Llk and no power is delivered C4
D2
D4
to the output.

Fig. 10. Mode 8 ( t7 ~ t8 )

 Mode 9 ( t8 ~ t9 ), freewheeling mode To reduce the losses incur by the isolation transformer, a
ferrite material with low saturation flux density is considered
At mode t = t8 , switch S4 is turned on with ZVS and the
for magnetic core with maximum magnetic flux Bmax of 0.2T
primary current I p freewheel though switch S2 and S4. The
(2000G). For a core with cross area Ac of 1.5cm2, the number
transformer secondary voltage Vs is zero and the output
of turns for primary side N p of the high frequency transformer
inductor voltage is discharged by the load.
is determined from [9]:
Lo

Vin (min) D
S1 S3 d3 Np = X 10 8 (1)
d1
C1 C3
D1 D3 2 Bmax ( G ) Ac ( cm 2 ) f s (Hz)
Llk
Vin RL
The transformer primary turn N p is chosen as 3 turns
Co
To meet the output voltage requirement and cater for
S2 d2
C2 S4 d4 voltage drop across circuit elements, the transformer secondary
C4
D2 D4
voltage Vsec should satisfy (2) [10].
Vo , (2)
Vsec
Dmax
Fig. 11. Mode 9 ( t8 ~ t9 )
With the duty cycle of 0.4, the output secondary voltage
Mode 10 ( t9 ~ t10 ), switch S1 ZVS Vo = Deff * Vsec . The number of turns for transformer secondary
At mode t = t9 , switch S2 is turned off and the primary N s is calculated from:
current charges the snubber capacitance C 2 of switch S2 and Vsec
discharge capacitance C1 of switch S1. When the snubber Ns = N p = 42 turns (3)
Vin (min)
capacitance C1 is completely discharge from Vin to 0, the body
diode d1 start to conduct to achieve zero voltage switching The voltage across the output filter inductor Lois ( nVin V0 )
condition for S1 eliminating FET device switching losses. At for the period Deff Ts is given by [11]:
this mode the transformer secondary voltage become zero and
the rectifier diodes D2 , D3 carrying current. (nVin Vo ) Deff
Lo
Lo = (4)
I L f s
S1 S3 d3
d1
C1 C3
D1 D2
For 20% output inductor current ripple I L , output filter
Llk
inductor is 1.605 mH
Vin RL
Co The selection of output filter capacitor is specified by the
output voltage ripple V o chosen as 0.25% (1V) of V o [11].
S2 d2 C2 S4 d4
C4
D3 Vo (1 Deff )
D4 Vc = = 0.95F (5)
16 f s 2CLo f s
Fig. 12. Mode 10 ( t9 ~ t10 ) The frequency for achieving ZVS switching resonance
between the stored energy in leakage inductance of the
III. PHASE-SHIFT FULL BRIDGE CONVERTER DESIGN transformer and the FET device (MOSFETs) junction
A 3kW high frequency phase-shift full bridge converter capacitance for all the four switches is similar and given by:
with the following specification is designed and simulated in 1
fr = (6)
Matlab/Simulink. 2 Llk C r
- Nominal input voltage, V in (nom ) = 48V
- Input voltage range, Vin ( range ) = 36V-60V Where Cr = 2Coss (tr ) + CTx , CTx is the transformer
- Output voltage, Vo = 400V capacitance and Coss (er ) is the FET energy stored in the
- Efficiency n 90% nonlinear drain to source output capacitance. The transition of
- Output current Io(max)= 7.5 A the voltage across the drain-source ( ) requires minimum
frequency of at least 1/4th of the resonant period ( Tr 4 ) i.e.
- Output voltage ripple V o = 1V
t d T r 4 . In this project, the superFET FCH043N60 was
- Output inductor current ripple I L = 1.5A
chosen haven satisfy the required switching characteristic for
- Switching frequency fs = 100kHz experimental implantation of the phase-shift full bridge
- Maximum duty cycle Dmax of 0.4 converter. The switch effective output capacitance is 730 pF
and transformer capacitance is taken as 500 pF . The total turn
on delay time td is 200 ns , the leakage inductance is calculated
from:
L lk = 4 t d 2 / 2 C r = 8.3 H (7)

IV. SIMULATION RESULTS

The steady state designed parameters of the phase-shift full
bridge dc-dc converter was used for open loop simulation in
Matlab/Simulink environment. The generated control gate
signal to the four switches (S1~S4) of the full bridge converter
is presented in Fig. 13 showing the phase shift features that
allows zero voltage switching, eliminating switching losses for
high efficiency delivery.
Fig. 15. Transformer secondary voltage and current

The phase-shift full bridge dc-dc converter output voltage

and current under full load operation is presented in Fig.16. The
open loop response shows that the system has transient voltage
overshoot at start up till about 0.2ms before it finally settled to
400V. The converter efficiency with different load condition
was measure and presented in Fig. 17. At rated load current, the
system attained 93% efficiency.

Fig. 13. Gating signal

The designed phase-shift converter performance was

analysed under different loading conditions. Presented in Fig.
14 is the converter transformer primary voltage and current at
full load [7.5A load current]. Also in Fig. 15 shows the
transformer secondary voltage and current at full load. The
transformer primary voltage takes two values of Vin during the
effective phase-shift duty cycle twice, one along the positive
plane +Vin and the other along the negative plane Vin in one Fig. 16. Full load output voltage and current
complete cycle. During the effective phase-shift duty cycle the
transformer secondary voltage takes a values of + nVin on the 100
positive plane and nVin on along the negative
80
Efficiency (%)

60

40

20

0
0 20 40 60 80 100
Load (%)
Fig. 17. % Load current Vs Efficiency

Fig. 14. Transformer primary voltage and current

 V. CONCLUSION
A ZVS phase-shifted full bridge dc-dc converter of 100 kHz
switching frequency has been designed and model in Simulink
environment. The switching stages of the phase-shift full bridge
dc-dc converter during power transfer in a complete switching
cycle was analyzed with circuit illustration. The steady state
circuit parameter for a 3kW converter was designed with the
circuit elements including the isolated transformer and the
performance of the system was verified in Matlab/Simulink
environment. The converter voltage, current waveforms and the
output power is satisfactory for the designed power rating. The
system performance was further analyzed under different
loading conditions and was able to deliver 93% efficiency at
rated load current of 7.5A.

REFERENCES
[1] S. Ang and A. Oliva, Power-switching converters: CRC press, 2005.
[2] Y. Xie, R. Ghaemi, J. Sun, and J. S. Freudenberg, "Model predictive
control for a full bridge DC/DC converter," Control Systems
Technology, IEEE Transactions on, vol. 20, pp. 164-172, 2012.
[3] Y. Jang, M. M. Jovanovi, and Y.-M. Chang, "A new ZVS-PWM full-
bridge converter," Power Electronics, IEEE Transactions on, vol. 18,
pp. 1122-1129, 2003.
[4] M. Hallworth, B. Potter, and S. A. Shirsavar, "Analytical calculation of
resonant inductance for zero voltage switching in phase-shifted full-
bridge converters," Power Electronics, IET, vol. 6, pp. 523-534, 2013.
[5] G.-B. Koo, G.-W. Moon, and M.-J. Youn, "Analysis and design of
phase shift full bridge converter with series-connected two
transformers," Power Electronics, IEEE Transactions on, vol. 19, pp.
411-419, 2004.
[6] G. Di Capua, S. A. Shirsavar, M. A. Hallworth, and N. Femia, "An
enhanced model for small-signal analysis of the phase-shifted full-
bridge converter," Power Electronics, IEEE Transactions on, vol. 30,
pp. 1567-1576, 2015.
[7] S. Khazraei, A. Rahmati, and A. Abrishamifar, "Small signal and large
signal charge control models for a phase-shifted PWM converter," in
Industrial Technology, 2008. ICIT 2008. IEEE International
Conference on, 2008, pp. 1-6.
[8] B.-R. Lin, K. Huang, and D. Wang, "Analysis and implementation of
full-bridge converter with current doubler rectifier," IEE Proceedings-
Electric Power Applications, vol. 152, pp. 1193-1202, 2005.
[9] N. Mohan and T. M. Undeland, Power electronics: converters,
applications, and design: John Wiley & Sons, 2007.
[10] J. Sabate, V. Vlatkovic, R. Ridley, F. Lee, and B. Cho, "Design
considerations for high-voltage high-power full-bridge zero-voltage-
switched PWM converter," in Proc. IEEE APEC, 1990, pp. 275-284.
[11] M. K. Kazimierczuk, Pulse-width modulated DC-DC power
converters: John Wiley & Sons, 2008.