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Search Results (2,155)

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14 pages, 1978 KiB  
Article
Similarity Analysis of Computer-Generated and Commercial Libraries for Targeted Biocompatible Coded Amino Acid Replacement
by Markus Meringer, Gerardo M. Casanola-Martin, Bakhtiyor Rasulev and H. James Cleaves
Int. J. Mol. Sci. 2024, 25(22), 12343; https://doi.org/10.3390/ijms252212343 (registering DOI) - 17 Nov 2024
Abstract
Many non-natural amino acids can be incorporated by biological systems into coded functional peptides and proteins. For such incorporations to be effective, they must not only be compatible with the desired function but also evade various biochemical error-checking mechanisms. The underlying molecular mechanisms [...] Read more.
Many non-natural amino acids can be incorporated by biological systems into coded functional peptides and proteins. For such incorporations to be effective, they must not only be compatible with the desired function but also evade various biochemical error-checking mechanisms. The underlying molecular mechanisms are complex, and this problem has been approached previously largely by expert perception of isomer compatibility, followed by empirical study. However, the number of amino acids that might be incorporable by the biological coding machinery may be too large to survey efficiently using such an intuitive approach. We introduce here a workflow for searching real and computed non-natural amino acid libraries for biosimilar amino acids which may be incorporable into coded proteins with minimal unintended disturbance of function. This workflow was also applied to molecules which have been previously benchmarked for their compatibility with the biological translation apparatus, as well as commercial catalogs. We report the results of scoring their contents based on fingerprint similarity via Tanimoto coefficients. These similarity scoring methods reveal candidate amino acids which could be substitutable into modern proteins. Our analysis discovers some already-implemented substitutions, but also suggests many novel ones. Full article
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13 pages, 1029 KiB  
Article
A Combination of Traditional and Mechanized Logging for Protected Areas
by Natascia Magagnotti, Benno Eberhard and Raffaele Spinelli
Forests 2024, 15(11), 2021; https://doi.org/10.3390/f15112021 (registering DOI) - 16 Nov 2024
Viewed by 192
Abstract
Teaming draught animals with modern forest machines may offer an innovative low-impact solution to biomass harvesting in protected areas. Machine traffic only occurs on pre-designated access corridors set 50 m apart, while trees are cut with chainsaws and dragged to the corridor’s edge [...] Read more.
Teaming draught animals with modern forest machines may offer an innovative low-impact solution to biomass harvesting in protected areas. Machine traffic only occurs on pre-designated access corridors set 50 m apart, while trees are cut with chainsaws and dragged to the corridor’s edge by draught horses. The operation presented in this study included one chainsaw operator, two draught horses with their driver, an excavator-based processor with its driver and a helper equipped with a chainsaw for knocking off forks and large branches, and a light forwarder (7 t) with his driver. Researchers assessed work productivity and harvesting cost through a time study repeated on 20 sample plots. Descriptive statistics were used to estimate productivity and cost benchmark figures, which were matched against the existing references for the traditional alternatives. The new system achieved a productivity in excess of 4 m3 over bark per scheduled hour (including delays). Harvesting cost averaged EUR 53 m−3, which was between 15% and 30% cheaper than the traditional alternatives. What is more, the new system increased labor and horse productivity by a factor of 2 and 7, respectively, which can effectively counteract the increasingly severe shortage of men and animals. Full article
22 pages, 3889 KiB  
Article
Malware Classification Using Few-Shot Learning Approach
by Khalid Alfarsi, Saim Rasheed and Iftikhar Ahmad
Information 2024, 15(11), 722; https://doi.org/10.3390/info15110722 - 11 Nov 2024
Viewed by 374
Abstract
Malware detection, targeting the microarchitecture of processors, has recently come to light as a potentially effective way to improve computer system security. Hardware Performance Counter data are used by machine learning algorithms in security mechanisms, such as hardware-based malware detection, to categorize and [...] Read more.
Malware detection, targeting the microarchitecture of processors, has recently come to light as a potentially effective way to improve computer system security. Hardware Performance Counter data are used by machine learning algorithms in security mechanisms, such as hardware-based malware detection, to categorize and detect malware. It is crucial to determine whether or not a file contains malware. Many issues have been brought about by the rise in malware, and businesses are losing vital data and dealing with other issues. The second thing to keep in mind is that malware can quickly cause a lot of damage to a system by slowing it down and encrypting a large amount of data on a personal computer. This study provides extensive details on a flexible framework related to machine learning and deep learning techniques using few-shot learning. Malware detection is possible using DT, RF, LR, SVM, and FSL techniques. The logic is that these algorithms make it simple to differentiate between files that are malware-free and those that are not. This indicates that their goal is to reduce the number of false positives in the data. For this, we use two different datasets from an online platform. In this research work, we mainly focus on few-shot learning techniques by using two different datasets. The proposed model has an 97% accuracy rate, which is much greater than that of other techniques. Full article
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16 pages, 20540 KiB  
Article
Evaluation of an Infinite-Level Inverter Operation Powered by a DC–DC Converter in Open and Closed Loop
by Nataly Gabriela Valencia Pavón, Alexander Aguila Téllez, Javier Rojas Urbano, Víctor Taramuel Obando and Edwin Guanga
Energies 2024, 17(22), 5593; https://doi.org/10.3390/en17225593 - 8 Nov 2024
Viewed by 313
Abstract
This paper evaluates the open- and closed-loop DC–DC converter operation within a DC coupling multilevel inverter architecture to obtain an infinite-level stepped sinusoidal voltage. Adding a cascade controller to the DC–DC converter should reduce the settling time and increase the number of levels [...] Read more.
This paper evaluates the open- and closed-loop DC–DC converter operation within a DC coupling multilevel inverter architecture to obtain an infinite-level stepped sinusoidal voltage. Adding a cascade controller to the DC–DC converter should reduce the settling time and increase the number of levels in the output voltage waveform; it could decrease the speed error and phase shift concerning the sinusoidal reference signal. The proposed methodology consists of implementing an experimental multilevel inverter with DC coupling through a single-phase bridge inverter energized from a BUCK converter. Trigger signals for the two converters are obtained from a control circuit based in an ATMEGA644P microcontroller to explore its capabilities in power electronics applications. A digital controller is also implemented to evaluate the operation of the BUCK converter in open and closed loop and observe its influence in the stepped sinusoidal output voltage. The evaluation is performed to energize a resistive load with common output voltage in multilevel inverters, i.e., 3, 5, 7, 11, and infinity levels. Results show that during the design stage, fast dynamic elements, like the storage capacitor, can be used to obtain a minimum THD because the settling time is sufficiently fast, the speed error remains small, and there is no need for a controller. A digital controller requires processing time, and although in theory it can reduce the settling time to a minimum, the processor introduces latency in the control signals generation, producing the opposite effect. Controller complexity of the digital controller must be considered because it increases processing time and influences the efficiency of the closed-loop operation. Full article
(This article belongs to the Special Issue Energy, Electrical and Power Engineering: 3rd Edition)
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23 pages, 4551 KiB  
Article
A Model-Based Optimization Method of ARINC 653 Multicore Partition Scheduling
by Pujie Han, Wentao Hu, Zhengjun Zhai and Min Huang
Aerospace 2024, 11(11), 915; https://doi.org/10.3390/aerospace11110915 - 7 Nov 2024
Viewed by 400
Abstract
ARINC 653 Part 1 Supplement 5 (ARINC 653P1-5) provides temporal partitioning capabilities for real-time applications running on the multicore processors in Integrated Modular Avionics (IMAs) systems. However, it is difficult to schedule a set of ARINC 653 multicore partitions to achieve a minimum [...] Read more.
ARINC 653 Part 1 Supplement 5 (ARINC 653P1-5) provides temporal partitioning capabilities for real-time applications running on the multicore processors in Integrated Modular Avionics (IMAs) systems. However, it is difficult to schedule a set of ARINC 653 multicore partitions to achieve a minimum processor occupancy. This paper proposes a model-based optimization method for ARINC 653 multicore partition scheduling. The IMA multicore processing system is modeled as a network of timed automata in UPPAAL. A parallel genetic algorithm is employed to explore the solution space of the IMA system. Owing to a lack of priori information for the system model, the configuration of genetic operators is self-adaptively controlled by a Q-learning algorithm. During the evolution, each individual in a population is evaluated independently by compositional model checking, which verifies each partition in the IMA system and combines all the schedulability results to form a global fitness evaluation. The experiments show that our model-based method outperforms the traditional analytical methods when handling the same task loads in the ARINC 653 multicore partitions, while alleviating the state space explosion of model checking via parallelization acceleration. Full article
(This article belongs to the Special Issue Aircraft Design and System Optimization)
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20 pages, 1585 KiB  
Article
Microbiological Analysis of Wild Lowbush Blueberries Harvested in Nova Scotia, Canada for the Fresh Produce Market
by Timothy Ells, Nancy Tregunno, Lihua Fan, Michele Elliot, Craig Doucette, Hugh Lyu and Alexa Jollimore
Microorganisms 2024, 12(11), 2251; https://doi.org/10.3390/microorganisms12112251 - 7 Nov 2024
Viewed by 466
Abstract
Canada is a leading producer of wild lowbush blueberries, most of which are mechanically harvested, washed, individually quick frozen (IQF), and bulk packaged. Still, some berries are harvested by more gentle methods and sold as fresh-packed products. These berries do not undergo a [...] Read more.
Canada is a leading producer of wild lowbush blueberries, most of which are mechanically harvested, washed, individually quick frozen (IQF), and bulk packaged. Still, some berries are harvested by more gentle methods and sold as fresh-packed products. These berries do not undergo a wash step, nor are subjected to antimicrobial treatments. The purpose of this study was to conduct a microbiological survey of berries harvested in the province of Nova Scotia to assess their potential for harborage of bacterial foodborne pathogens. A combination of standardized plate count methods and 3M-Petrifilm protocols were used to enumerate total aerobic mesophilic bacteria (APC), yeasts and molds (YMC), coliforms, and generic E. coli, the latter being an indicator of fecal contamination. Overall, APC and YMC levels were 1.2 and 0.5 log greater, respectively, for berries collected early in the harvest season versus those acquired late season and varied significantly (p < 0.05) between farm (location) and harvest practices used. Berries harvested by our team using sanitized hand rakes (SH) had consistently lower APC and YMC levels than those harvested by farm crews. Yet, when gentle harvesting (GH) methods (hand-raking, walk-behind or modified mechanical harvesters) were employed on farms, lower numbers were generally observed compared to berries harvested by traditional tractor-mounted mechanized harvesters (MH). The presence of coliforms (and their levels) was also impacted by the harvest method, with detection rates of ~29%, 73%, and 92% in SH, GH, and MH samples, respectively. Mean counts were < 2.5 log10 CFU/g for both SH and GH berries, but significantly higher (p < 0.05) on MH berries (3.6 log10 CFU/g). Although ~56% of all berry samples collected (n = 350) contained coliforms, only 12 were positive for E. coli, 9 of which were MH samples. Only the latter had numbers > 2 log10 CFU/g, but none tested positive for Shiga toxin-producing serotype O157 (STEC O157) or Salmonella spp. when using internationally recognized selective enrichment and plating methods. ATP luminescence was used to assess the general hygiene of processing lines, whereby “hot spots” for microbial activity were identified, even after cleaning., Standard selective enrichment and plating methods were used for the detection of Listeria monocytogenes on 61 swab samples taken from berry totes or conveyor belts at different times during processing; 4 swabs tested positive for L. monocytogenes. However, the pathogen could not be detected by direct plating on selective agar without prior enrichment; this indicated its numbers were low. The results from this work demonstrated that alternative gentle harvest methods can reduce microbial numbers on wild blueberries. Although the frequency of fecal contamination in berry samples appeared to be low and targeted human pathogens were not detected; this represents a single study conducted over one harvest season. Therefore, it would be prudent for processors to seek effective antimicrobial technologies prior to packaging, while consumers should use caution and thoroughly wash produce before consumption. Where sporadic detection of L. monocytogenes was observed on environmental samples from the processing line, processors must ensure that effective sanitation programs are implemented to avoid potential food safety risks. Full article
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10 pages, 2297 KiB  
Article
New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA
by José Rangel, Esteban Anides, Eduardo Vázquez, Giovanny Sanchez, Juan-Gerardo Avalos, Gonzalo Duchen and Linda K. Toscano
Mathematics 2024, 12(22), 3472; https://doi.org/10.3390/math12223472 - 7 Nov 2024
Viewed by 428
Abstract
During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Despite achieving significant results, improvement in these factors [...] Read more.
During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Despite achieving significant results, improvement in these factors is still a challenging task. Recently, an emerging computational area has been seen as a potential solution to improving the performance of conventional binary circuits. In particular, this area uses a method based on spiking neural P systems (SN P) to create arithmetic circuits, such as adders, subtractors, multipliers, and divisors, since these components are vital in many IoT applications. To date, several efforts have been dedicated to decreasing the number of neurons and synapses to create compact circuits. However, processing speed is a persistent issue. In this work, we propose four compact arithmetic circuits with high processing speeds. To evaluate their performance, we designed a neuromorphic processor that is capable of performing four operations using dynamic connectivity. As a consequence, the proposed neuromorphic processor achieves higher processing speeds by maintaining low area consumption in comparison with the existing approaches. Full article
(This article belongs to the Special Issue Methods, Analysis and Applications in Computational Neuroscience)
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18 pages, 6358 KiB  
Article
Implementation of an Image Tampering Detection System with a CMOS Image Sensor PUF and OP-TEE
by Tatsuya Oyama, Manami Hagizaki, Shunsuke Okura and Takeshi Fujino
Sensors 2024, 24(22), 7121; https://doi.org/10.3390/s24227121 - 5 Nov 2024
Viewed by 394
Abstract
Since image recognition systems use image data acquired by image sensors for analysis by AI technology, an important security issue is guaranteeing the authenticity of data transmitted from image sensors to successfully perform inference using AI. There have been reports of physical attacks [...] Read more.
Since image recognition systems use image data acquired by image sensors for analysis by AI technology, an important security issue is guaranteeing the authenticity of data transmitted from image sensors to successfully perform inference using AI. There have been reports of physical attacks on image sensor interfaces by tampering with images to cause misclassifications in AI classification results. As a countermeasure against these attacks, it is effective to add authenticity to image data with a message authentication code (MAC). For the implementation of this, it is important to have technologies for generating MAC keys on image sensors and to create an environment for secure MAC verification on the host device. For MAC key generation, we used the CIS-PUF technology, which generates MAC keys from PUF responses and random numbers from CMOS image sensor variations. For the secure MAC verification, we used TEE technology, which executes security-critical processes in an environment isolated from the normal operating system. In this study, we propose and demonstrate an image tampering detection system based on MAC verification with CIS-PUF and OP-TEE in an open portable TEE on an ARM processor. In the experiments, we demonstrated a system that computed and transmitted MAC for captured images using the CIS-PUF key and then performed MAC verification in the secure world of the OP-TEE. Full article
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26 pages, 5125 KiB  
Article
Power Battery Recycling Model of Closed-Loop Supply Chains Considering Different Power Structures Under Government Subsidies
by Fei Zeng, Zhiping Lu and Chengyu Lu
Sustainability 2024, 16(21), 9589; https://doi.org/10.3390/su16219589 - 4 Nov 2024
Viewed by 591
Abstract
With the rapid growth of the electric vehicle industry, the recycling of power batteries has attracted significant attention. In light of current circumstances, the question of how the government can incentivize relevant stakeholders to actively engage in recycling and improve its efficiency has [...] Read more.
With the rapid growth of the electric vehicle industry, the recycling of power batteries has attracted significant attention. In light of current circumstances, the question of how the government can incentivize relevant stakeholders to actively engage in recycling and improve its efficiency has become increasingly pressing. In this context, this study analyses and develops four closed-loop supply chain recycling models to investigate how different government subsidy recipients under varying power structures influence recycling efficiency, profitability, and the overall supply chain structures. The following conclusions are derived from numerical simulations: (1) Government subsidies serve to elevate recycling prices, expand profit margins, and consequently boost the volume of recycled batteries, thus incentivizing corporate engagement in recycling initiatives. (2) When the processor assumes the role of the leader in the Stackelberg game framework, it can maximize the overall efficiency and profitability of the supply chain. (3) The sensitivity coefficient and the competition coefficient are closely interrelated, exerting opposing impacts on the recycling decision made by enterprises. (4) The supply chain leader plays a crucial role in ensuring orderly supply chain development, with government subsidies of the supply chain being transmitted to its members through the leader. Consequently, this study offers a theoretical foundation for the government to enhance policy-making and for enterprises to make informed decisions. It also holds significant practical relevance in addressing the challenges associated with power battery recycling. Full article
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22 pages, 762 KiB  
Article
BTIP: Branch Triggered Instruction Prefetcher Ensuring Timeliness
by Wenhai Lin, Yiquan Lin, Yiquan Chen, Shishun Cai, Zhen Jin, Jiexiong Xu, Yuzhong Zhang and Wenzhi Chen
Electronics 2024, 13(21), 4323; https://doi.org/10.3390/electronics13214323 - 4 Nov 2024
Viewed by 504
Abstract
In CPU microarchitecture, caches store frequently accessed instructions and data by exploiting their locality, reducing memory access latency and improving application performance. However, contemporary applications with large code footprints often experience frequent Icache misses, which significantly degrade performance. Although Fetch-Directed Instruction Prefetching (FDIP) [...] Read more.
In CPU microarchitecture, caches store frequently accessed instructions and data by exploiting their locality, reducing memory access latency and improving application performance. However, contemporary applications with large code footprints often experience frequent Icache misses, which significantly degrade performance. Although Fetch-Directed Instruction Prefetching (FDIP) has been widely adopted in commercial processors to reduce Icache misses, our analysis reveals that FDIP still suffers from Icache misses caused by branch mispredictions and late prefetch, leaving considerable opportunity for performance optimization. Priority-Directed Instruction Prefetching (PDIP) has been proposed to reduce Icache misses caused by branch mispredictions in FDIP. However, it neglects Icache misses due to late prefetch and suffers from high storage overhead. In this paper, we proposed a branch-triggered instruction prefetcher (BTIP), which aims to prefetch Icache lines that FDIP cannot efficiently handle, including the Icache misses due to branch misprediction and late prefetch. We also introduce a novel Branch Target Buffer (BTB) organization, BTIP BTB, which stores prefetch metadata and reuses information from existing BTB entries, effectively reducing storage overhead. We implemented BTIP on the Champsim simulator and evaluated BTIP in detail using traces from the 1st Instruction Prefetching Championship (IPC-1). Our evaluation shows that BTIP outperforms both FDIP and PDIP. Specifically, BTIP reduces Icache misses by 38.0% and improves performance by 5.1% compared to FDIP. Additionally, BTIP outperforms PDIP by 1.6% while using only 41.9% of the storage space required by PDIP. Full article
(This article belongs to the Special Issue Computer Architecture & Parallel and Distributed Computing)
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14 pages, 590 KiB  
Article
Self-Reported Difficulty with and Assistance Needed by People with Spinal Cord Injury to Prepare Meals at Home
by Katherine Froehlich-Grobe
Int. J. Environ. Res. Public Health 2024, 21(11), 1463; https://doi.org/10.3390/ijerph21111463 - 1 Nov 2024
Viewed by 558
Abstract
Individuals with spinal cord injury (SCI) experience an increased risk for obesity and cardiometabolic disease. Recommendations to prevent and treat obesity for those with SCI follow those of the US Department of Agriculture to adopt a healthy eating pattern that includes eating a [...] Read more.
Individuals with spinal cord injury (SCI) experience an increased risk for obesity and cardiometabolic disease. Recommendations to prevent and treat obesity for those with SCI follow those of the US Department of Agriculture to adopt a healthy eating pattern that includes eating a variety of fruits, vegetables, grains, dairy, and protein, plus limiting added sugars, saturated fats, and sodium. Yet, people with SCI eat too many calories, fat, and carbohydrates and too few fruits, vegetables, and whole grains. The study is based on secondary analyses of SCI participants (n = 122) who enrolled in a weight loss study to determine how SCI may impact their ability to prepare food at home. We hypothesize those with higher-level spinal injuries (specifically, those with cervical versus those with thoracic or lumbar/sacral injuries) experience significantly greater difficulty and are more likely to rely on others’ assistance to perform meal preparation tasks. Physiologic (weight, BMI, blood pressure, hemoglobin A1c) and self-reported data (demographic plus responses to the Life Habits Short Survey and meal prep items) were collected at baseline and qualitative data were obtained from a subsample after the intervention during phone interviews. Participants’ average age was 50 ± 14.7 years old, they lived with SCI for an average of 13.0 ± 13.1 years, and their average BMI was 32.0 ± 6.5. Participants were predominantly white (76.1%) men (54.1%) who had some college education (76.3%), though only 28.8% worked. A substantial proportion of respondents (30% to 68%) reported difficulty across the 13 tasks related to purchasing and preparing meals, with a proxy reported as the most common assistance type used across all tasks (17% to 42%). Forty-nine percent reported difficulty preparing simple meals, with 29% reporting a proxy does the task. More than half reported difficulty using the oven and stove, though between 60% to 70% reported no difficulty using other kitchen appliances (e.g., coffee machine, food processor, can opener), the refrigerator, or microwave. There was a significant difference in kitchen function by injury level. Those living with cervical-level injuries had significantly greater limitations than those with thoracic-level injuries. Spouses, other family members, and caregivers were most likely to serve as proxies and these individuals exerted both positive and negative influences on respondents’ dietary intake, based on qualitative data obtained during interviews. The results suggest that many people living with SCI experience functional and environmental barriers that impact their ability to prepare food and use kitchen appliances. Future research should examine how SCI-related functional limitations, transportation access, accessibility of the kitchen, ability to use appliances, availability of financial resources, and assistance by others to prepare foods impact people’s ability to follow a healthy eating pattern. Full article
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14 pages, 2999 KiB  
Article
AI-Aided Robotic Wide-Range Water Quality Monitoring System
by Ameen Awwad, Ghaleb A. Husseini and Lutfi Albasha
Sustainability 2024, 16(21), 9499; https://doi.org/10.3390/su16219499 - 31 Oct 2024
Viewed by 520
Abstract
Waterborne illnesses lead to millions of fatalities worldwide each year, particularly in developing nations. In this paper, we introduce a comprehensive system designed for the autonomous early detection of viral outbreaks transmitted through water to ensure sustainable access to healthy water resources, especially [...] Read more.
Waterborne illnesses lead to millions of fatalities worldwide each year, particularly in developing nations. In this paper, we introduce a comprehensive system designed for the autonomous early detection of viral outbreaks transmitted through water to ensure sustainable access to healthy water resources, especially in remote areas. The system utilizes an autonomous water quality monitoring setup consisting of an airborne water sample collector, an autonomous sample processor, and an artificial intelligence-aided microscopic detector for risk assessment. The proposed system replaces the time-consuming conventional monitoring protocol by automating sample collection, sample processing, and pathogen detection. Furthermore, it provides a safer processing method against the spillage of contaminated liquids and potential resultant aerosols during the heat fixation of specimens. A morphological image processing technique of light microscopic images is used to segment images, assisting in selecting a unified appropriate input segment size based on individual blob areas of different bacterial cultures. The dataset included harmful pathogenic bacteria (A. baumanii, E. coli, and P. aeruginosa) and harmless ones found in drinking water and wastewater (E. faecium, L. paracasei, and Micrococcus spp.). The segmented labeled dataset was used to train deep convolutional neural networks to automatically detect pathogens in microscopic images. To minimize prediction error, Bayesian optimization was applied to tune the hyperparameters of the networks’ architecture and training settings. Different convolutional networks were tested in accordance with different required output labels. The neural network used to classify bacterial cultures as harmful or harmless achieved an accuracy of 99.7%. The neural network used to identify the specific types of bacteria achieved a cumulative accuracy of 93.65%. Full article
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19 pages, 7625 KiB  
Article
A Proof-of-Concept Open-Source Platform for Neural Signal Modulation and Its Applications in IoT and Cyber-Physical Systems
by Arfan Ghani
IoT 2024, 5(4), 692-710; https://doi.org/10.3390/iot5040031 - 29 Oct 2024
Viewed by 483
Abstract
This paper presents the design, implementation, and characterization of a digital IoT platform capable of generating brain rhythm frequencies using synchronous digital logic. Designed with the Google SkyWater 130 nm open-source process design kit (PDK), this platform emulates Alpha, Beta, and Gamma rhythms. [...] Read more.
This paper presents the design, implementation, and characterization of a digital IoT platform capable of generating brain rhythm frequencies using synchronous digital logic. Designed with the Google SkyWater 130 nm open-source process design kit (PDK), this platform emulates Alpha, Beta, and Gamma rhythms. As a proof of concept and the first of its kind, this device showcases its potential applications in both industrial and academic settings. The platform was integrated with an IoT device to optimize and accelerate research and development efforts in embedded systems. Its cost-effective and efficient performance opens opportunities for real-time neural signal processing and integrated healthcare. The presented digital platform serves as a valuable educational tool, enabling researchers to engage in hands-on learning and experimentation with IoT technologies and system-level hardware–software integration at the device level. By utilizing open-source tools, this research demonstrates a cost-effective approach, fostering innovation and bridging the gap between theoretical knowledge and practical application. Furthermore, the proposed system-level design can be interfaced with various serial devices, Wi-Fi modules, ARM processors, and mobile applications, illustrating its versatility and potential for future integration into broader IoT ecosystems. This approach underscores the value of open-source solutions in driving technological advancements and addressing skills shortages. Full article
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21 pages, 2544 KiB  
Article
An Energy-Efficient Dynamic Feedback Image Signal Processor for Three-Dimensional Time-of-Flight Sensors
by Yongsoo Kim, Jaehyeon So, Chanwook Hwang, Wencan Cheng and Jong Hwan Ko
Sensors 2024, 24(21), 6918; https://doi.org/10.3390/s24216918 - 28 Oct 2024
Viewed by 546
Abstract
With the recent prominence of artificial intelligence (AI) technology, various research outcomes and applications in the field of image recognition and processing utilizing AI have been continuously emerging. In particular, the domain of object recognition using 3D time-of-flight (ToF) sensors has been actively [...] Read more.
With the recent prominence of artificial intelligence (AI) technology, various research outcomes and applications in the field of image recognition and processing utilizing AI have been continuously emerging. In particular, the domain of object recognition using 3D time-of-flight (ToF) sensors has been actively researched, often in conjunction with augmented reality (AR) and virtual reality (VR). However, for more precise analysis, high-quality images are required, necessitating significantly larger parameters and computations. These requirements can pose challenges, especially in developing AR and VR technologies for low-power portable devices. Therefore, we propose a dynamic feedback configuration image signal processor (ISP) for 3D ToF sensors. The ISP achieves both accuracy and energy efficiency through dynamic feedback. The proposed ISP employs dynamic area extraction to perform computations and post-processing only for pixels within the valid area used by the application in each frame. Additionally, it uses dynamic resolution to determine and apply the appropriate resolution for each frame. This approach enhances energy efficiency by avoiding the processing of all sensor data while maintaining or surpassing accuracy levels. Furthermore, These functionalities are designed for hardware-efficient implementation, improving processing speed and minimizing power consumption. The results show a maximum performance of 178 fps and a high energy efficiency of up to 123.15 fps/W. When connected to the hand pose estimation (HPE) accelerator, it demonstrates an average mean squared error (MSE) of 10.03 mm, surpassing the baseline ISP value of 20.25 mm. Therefore, the proposed ISP can be effectively utilized in low-power, small form-factor devices. Full article
(This article belongs to the Special Issue Vision Sensors for Object Detection and Tracking)
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20 pages, 6342 KiB  
Article
ASIP Performance Enhancement by Hazard Control through Scoreboard
by Xinbing Zhou, Yi Man, Peng Hao, Wei Chen, Bo Yang, Baoguo Ding and Dake Liu
Micromachines 2024, 15(11), 1287; https://doi.org/10.3390/mi15111287 - 23 Oct 2024
Viewed by 476
Abstract
The application-specific instruction set processor (ASIP) has been gradually accepted in AI, communication, media, game and industry control. The digital signal processor (DSP) is a typical ASIP, whose benefits include high performance in specific domains, low power consumption, high flexibility and low silicon [...] Read more.
The application-specific instruction set processor (ASIP) has been gradually accepted in AI, communication, media, game and industry control. The digital signal processor (DSP) is a typical ASIP, whose benefits include high performance in specific domains, low power consumption, high flexibility and low silicon consumption. One of the challenges for DSP design is to handle problems induced by datapath acceleration. The datapath acceleration (instruction fusion, black box instructions) induces control complexities. To most efficiently utilize hardware, control challenges can be summarized as RAW (Read-After-Write) handling, hardware hazard handling, and WAW (Write-After-Write) handling. Both an advanced compiler and hardware hazard handler can be used as solutions. In this paper, we introduced both solutions and exposed the benefits from the hardware solution. The benefits include utilizing low silicon to achieve higher performance and program memory reduction on chip. In summary, our solution only uses 0.91% extra silicon area yet achieves 32.75% performance improvement. So, the overall performance-to-cost ratio could be evaluated as 32%. Full article
(This article belongs to the Topic Advanced Integrated Circuit Design and Application)
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