「Antonio Mastrandrea」に一致するユーザー プロフィール
Antonio MastrandreaSapienza University of Rome 確認したメール アドレス: uniroma1.it 被引用数: 458 |
Design and evaluation of buffered triple modular redundancy in interleaved-multi-threading processors
Fault management in digital chips is a crucial aspect of functional safety. Significant work
has been done on gate and microarchitecture level triple modular redundancy, and on …
has been done on gate and microarchitecture level triple modular redundancy, and on …
Evaluation of dynamic triple modular redundancy in an interleaved-multi-threading risc-v core
Functional safety is a key requirement in several application domains in which microprocessors
are an essential part. A number of redundancy techniques have been developed with …
are an essential part. A number of redundancy techniques have been developed with …
Klessydra-t: designing vector coprocessors for multithreaded edge-computing cores
A Cheikh, S Sordillo, A Mastrandrea, F Menichelli… - IEEE Micro, 2021 - ieeexplore.ieee.org
Computation-intensive kernels, such as convolutions, matrix multiplication, and Fourier
transform, are fundamental to edge-computing AI, signal processing, and cryptographic …
transform, are fundamental to edge-computing AI, signal processing, and cryptographic …
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops
The assessment of noise margins and the related probability of failure in digital cells has
growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting …
growingly become essential, as nano-scale MOSFET and FinFET technologies are confronting …
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment
M Barbirotta, A Mastrandrea… - … on Defect and Fault …, 2020 - ieeexplore.ieee.org
Fault tolerance is a key requirement in several application domains of embedded processors
cores. In a wide variety of applications, however, a full protection against faults occurring in …
cores. In a wide variety of applications, however, a full protection against faults occurring in …
Fault-tolerant hardware acceleration for high-performance edge-computing nodes
High-performance embedded systems with powerful processors, specialized hardware
accelerators, and advanced software techniques are all key technologies driving the growth of …
accelerators, and advanced software techniques are all key technologies driving the growth of …
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes
A Cheikh, G Cerutti, A Mastrandrea… - … in Electronics Pervading …, 2019 - Springer
Internet-of-Things end-nodes demand low power processing platforms characterized by
heterogeneous dedicated units, controlled by a processor core running multiple control threads. …
heterogeneous dedicated units, controlled by a processor core running multiple control threads. …
A voltage-based leakage current calculation scheme and its application to nanoscale MOSFET and FinFET standard-cell designs
Z Abbas, A Mastrandrea… - IEEE Transactions on Very …, 2014 - ieeexplore.ieee.org
Logic-level estimators of leakage currents, in nanoscale standard-cell-based designs, are
relevant for the dramatic speed advantage with respect to analog SPICE-level simulation. We …
relevant for the dramatic speed advantage with respect to analog SPICE-level simulation. We …
A Fault Tolerant soft-core obtained from an Interleaved-Multi-Threading RISC-V microprocessor design
Introducing Fault Tolerance (FT) in designs implemented with commercial-off-the-shelf (COTS)
components, such as FPGAs, is very interesting because they are orders of magnitude …
components, such as FPGAs, is very interesting because they are orders of magnitude …
Efficient mathematical accelerator design coupled with an interleaved multi-threading RISC-V microprocessor
A Cheikh, S Sordillo, A Mastrandrea… - … in Electronics Pervading …, 2020 - Springer
Interleaved multi-threaded architectures (IMT) have proven to be an advantageous solution
to maximize the pipeline utilization, when it comes to executing parallel applications, as …
to maximize the pipeline utilization, when it comes to executing parallel applications, as …