Decimal arithmetic

R Hutty - Z80 Assembly Language Programming for Students, 1981 - Springer
… The half-carry flag is set to 1 if an add instruction produces a carry out of the right nibble
of a register, otherwise the flag is set to O. Also, the half-carry flag is set to 1 if a subtract …

Side channel analysis of AVR XMEGA crypto engine

I Kizhvatov - Proceedings of the 4th Workshop on Embedded …, 2009 - dl.acm.org
… Direction is controlled by the halfcarry flag of the µC’s status register. Encryption/decryption
is done as follows: … the CPU half-carry flag is set to 0 for encryption or to 1 for decryption; …

An optimization of traditional CPU emulation techniques for execution on a quantum computer

J Fitzjohn, G Wilson, D Vicinanza… - Quantum Information …, 2024 - Springer
… For example, the half-carry flag method shown here works for an increment instruction as
we know if the four least significant bits are 0 (so reflecting the half-carry). Conversely, the four …

An analysis of fault effects and propagations in AVR microcontroller ATmega103 (L)

A Rohani, HR Zarandi - 2009 International Conference on …, 2009 - ieeexplore.ieee.org
This paper presents an analysis of the effects and propagations of transient faults by
simulation-based fault injection into the AVR microcontroller. This analysis is done by injecting …

Flag and Register Array Based High Performance Instruction Set Architecture of Embedded Processor

B Pandey, S Jain, M Kumar - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
Here, assumption is that if we add 8 numbers from register array then it takes 120ns when
execution time is 5ns and register access time is 10ns. If we add same 8 number using one by …

Design an Improved Encrypting Key Pad Using AVR-ATXMEGA Microcontroller

NV Manaf, AH Navin, MK Mirnia - … International Conference on …, 2010 - ieeexplore.ieee.org
… round is executed, and the half carry flag (H) in the CPU status register determines whether
encryption or decryption is performed. If the half-carry flag is set, decryption is performed and …

[PDF][PDF] –Low-power, High-speed CMOS Process Technology–Fully Static Operation• Power Consumption at 4 MHz, 3V, 25 C–Active: 3.0 mA–Idle Mode: 1.0 mA

OA Comparator, PS UART - gegusch.de
Description The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR
RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S8515 …

[PDF][PDF] Creating Efficient C Code for the MC68HC08

S Robb - East Kilbride, Scotland: Motorola Inc, 2000 - nxp.jp
The C programming language is a powerful, flexible and potentially portable high-level
programming language. These and other features, such as support for low-level operations, …

[PDF][PDF] UM008003-1202 Overview

D Bus, ID Bus - alphaengineeringlabs.com
Figure 5 depicts the timing during an M1 (opcode fetch) cycle. The PC is placed on the
address bus at the beginning of the M1 cycle. One half clock cycle later the MREQ signal goes …

[引用][C] Appendix D Instruction glossary

AI Course - Elsevier