A design of 10-bit 25-MS/s SAR ADC using separated clock frequencies with high speed comparator in 180nm CMOS
HN Minh, DN Quoc, T Hoang - 2015 International Conference …, 2015 - ieeexplore.ieee.org
A design of a 10-bit 25 MS/s Successive Approximation Register (SAR) Analog to Digital
Converter (ADC) that uses improved dynamic comparator has been introduced in this paper …
Converter (ADC) that uses improved dynamic comparator has been introduced in this paper …
A design of 10-bit 25-MS/s SAR ADC using separated clock frequencies with high speed comparator in 180nm CMOS
HN Minh, DN Quoc, T Hoang - 2015 International Conference on Advanced … - infona.pl
A design of a 10-bit 25 MS/s Successive Approximation Register (SAR) Analog to Digital
Converter (ADC) that uses improved dynamic comparator has been introduced in this paper …
Converter (ADC) that uses improved dynamic comparator has been introduced in this paper …