Rohde et al., 2020 - Google Patents

Improving HLS generated accelerators through relaxed memory access scheduling

Rohde et al., 2020

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Document ID
17061295322857244907
Author
Rohde J
Müller K
Hochberger C
Publication year
Publication venue
2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Snippet

High-Level-Synthesis can be used to generate hardware accelerators for compute intense software parts (so called kernels). For meaningful acceleration, such kernels should be able to autonomously access the memory. Unfortunately, such memory accesses can constitute …
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Classifications

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    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
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