WO2022073518A1 - 一种叠层电池及其制作方法 - Google Patents

一种叠层电池及其制作方法 Download PDF

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WO2022073518A1
WO2022073518A1 PCT/CN2021/122897 CN2021122897W WO2022073518A1 WO 2022073518 A1 WO2022073518 A1 WO 2022073518A1 CN 2021122897 W CN2021122897 W CN 2021122897W WO 2022073518 A1 WO2022073518 A1 WO 2022073518A1
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layer
hole transport
transport layer
perovskite
cell
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PCT/CN2021/122897
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French (fr)
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徐琛
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隆基绿能科技股份有限公司
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Priority to US18/029,271 priority Critical patent/US12058876B2/en
Priority to EP21877035.2A priority patent/EP4207313A4/en
Publication of WO2022073518A1 publication Critical patent/WO2022073518A1/zh

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Definitions

  • the present application relates to the field of photovoltaic technology, and in particular, to a tandem battery and a manufacturing method thereof.
  • Organic-inorganic hybrid perovskite solar cells have attracted worldwide attention as new high-efficiency and low-cost solar cells.
  • the photoelectric conversion efficiency of perovskite cells has rapidly climbed from 3.8% in 2009 to more than 25%, which is close to the efficiency of commercial silicon-based solar cells.
  • Perovskite solar cells have wide band gaps and can be used as top cells of tandem cells.
  • a perovskite solar cell is stacked with a bottom cell with a textured structure, how to improve the hole transport performance of the hole transport layer, thereby improving the fill factor and conversion efficiency of the tandem cell, has become a focus of the tandem cell. .
  • the purpose of the present application is to provide a tandem battery to improve the hole transport performance of the tandem battery.
  • the present application provides a stacked battery.
  • the stacked battery includes a bottom cell, a hole transport layer formed on the bottom cell, a perovskite absorption layer formed on the hole transport layer, and a transparent conductive layer formed over the perovskite absorption layer.
  • the material of the hole transport layer includes a semiconductor material of p-type delafossite structure, and the top energy level of the valence band of the hole transport layer gradually decreases in the direction away from the bottom cell.
  • the material of the hole transport layer formed on the bottom cell includes a semiconductor material of p-type delafossite structure.
  • the top energy level of the valence band of the hole transport layer gradually decreases. Closer, it can replace the p-type heavily doped layer of the tunneling composite layer and the n-type heavily doped layer on the bottom cell to form a tunneling composite interface, thereby omitting the tunneling composite layer of the tandem battery and simplifying the process of the tandem battery.
  • the process difficulty is reduced, and compared with the structure of the tunneling composite layer, the contact interface between the hole transport layer and the tunneling composite layer is reduced, and the interface recombination of carriers is reduced.
  • the gradient energy level of the hole transport layer is beneficial to the transport of hole carriers, thereby improving the photoelectric conversion efficiency of solar cells.
  • the general chemical formula of the p-type delafossite-structured semiconductor material is AB ⁇ C x , including one or more of Cu + , Ag + , Pd + , Sr + , and Pt +
  • B includes one or more of B 3+ , Al 3+ , Ga 3+ , In 3+ , Cr 3+ , Fe 3+ , Sc 3+ and trivalent rare earth cations
  • ⁇ is between 0.9-1.1
  • C is an oxygen group element, including one or more of O, S, Se, Te
  • x is between 1.95-2.6
  • ⁇ is between 0.9-1.1.
  • the polarizability of the A ions is close to the polarizability of the halide ions in the perovskite material forming the perovskite absorption layer, so that it has a strong coordinating force and can reduce the
  • the interface contact defect between the hole transport layer and the perovskite absorber layer improves the interface contact performance, thereby improving the hole transport ability and photoelectric conversion efficiency of the tandem battery.
  • the content of element B in the hole transport layer increases sequentially from the direction away from the perovskite absorption layer to the direction close to the perovskite absorption layer, and the valence band of the hole transport layer increases.
  • the top energy level gradually decreases.
  • the thickness of the above hole transport layer is 5 nm ⁇ 100 nm.
  • the range of the top energy level of the valence band of the hole transport layer is -4.5eV ⁇ -5.4eV.
  • the top layer of the bottom cell is an n-type heavily doped layer.
  • the n-type heavily doped layer is in contact with the hole transport layer to form a carrier recombination interface.
  • the bottom cell can be an n-type cell or a p-type cell.
  • the n-type heavily doped layer, its underlying passivation layer and the bottom cell form a passivation cell structure, which can passivate the contact, reduce the unfavorable recombination of carriers, and improve the photoelectric conversion efficiency of the bottom cell;
  • the surface of the n-type heavily doped layer and the hole transport layer close to the bottom cell forms a tunneling recombination interface, which realizes the tunneling recombination of carriers between the bottom cell and the top cell.
  • the above-mentioned tandem cell further includes a passivation layer between the bottom cell and the n-type heavily doped layer.
  • the passivation layer can better passivate the bottom battery and inhibit unfavorable carrier recombination.
  • the above-mentioned bottom cells are crystalline silicon bottom cells, polycrystalline silicon bottom cells, ingot monocrystalline silicon bottom cells, copper indium gallium selenide bottom cells, perovskite bottom cells, gallium arsenide bottom cells, organic photovoltaics Either of the bottom batteries.
  • both the hole transport layer and the perovskite absorption layer have adjustable band gaps, they can be matched with the above-mentioned various bottom cell currents, thereby obtaining a tandem cell with high conversion efficiency.
  • the present application further provides a method for manufacturing the above-mentioned laminated battery.
  • the manufacturing method of the laminated battery includes:
  • a hole transport layer is formed on the bottom cell by a vacuum deposition process.
  • the material of the hole transport layer includes a semiconductor material with a p-type delafossite structure. In the direction away from the bottom cell, the top energy level of the valence band of the hole transport layer gradually increases. reduce;
  • An electron transport layer and a transparent conductive layer are formed on the perovskite absorber layer.
  • the above vacuum deposition process is a magnetron sputtering process, a laser pulse deposition process or a thermal evaporation coating process.
  • forming a perovskite absorber layer on the hole transport layer includes:
  • Lead iodide and cesium bromide are formed on the hole transport layer by co-evaporation;
  • the perovskite material thin film is annealed to form a perovskite absorber layer.
  • FIG. 1 is a schematic structural diagram of a stacked battery provided in an embodiment of the present application
  • FIGS. 2a and 2b are schematic diagrams of crystal structures of semiconductor materials with a p-type delafossite structure in embodiments of the present application, wherein a is the first crystal structure of the semiconductor material with a p-type delafossite structure, and b is a p-type delafossite structure.
  • FIG. 3 is a schematic structural diagram of an n-type silicon heterojunction-perovskite tandem battery provided by an embodiment of the present application;
  • 4 to 16 are schematic diagrams of states of various stages of the fabrication process of the n-type silicon heterojunction-perovskite tandem battery provided by the embodiments of the present application;
  • Fig. 17a is a schematic front view of the n-type silicon heterojunction-perovskite tandem cell shown in Fig. 3;
  • Fig. 17b is a schematic view of the back side of the n-type silicon heterojunction-perovskite tandem cell shown in Fig. 3;
  • FIG. 21 is a schematic diagram of the energy band of the stacked battery provided by Comparative Example 1 and Comparative Example 2;
  • FIG. 22 is a schematic diagram of the energy band of the stacked battery provided by the embodiment of the present application.
  • 100-bottom cell 101-n-type single crystal silicon substrate, 102-first passivation layer, 103-second passivation layer, 104-n-type doped layer, 105-p-type doped layer, 106-first Transparent conductive layer, 210-passivation layer, 220-n-type heavily doped layer, 310-hole transport layer, 320-perovskite absorber layer, 331-electron transport interface layer, 332-leakage repair layer, 333-electron Transmission layer, 340-transparent conductive layer, 341-second transparent conductive layer, 400-electrode.
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect.
  • words “first”, “second” and the like do not limit the quantity and execution order, and the words “first”, “second” and the like are not necessarily different.
  • At least one means one or more
  • plural means two or more.
  • And/or which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated objects are an “or” relationship.
  • At least one item(s) below” or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • At least one (a) of a, b or c may represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a combination of a, b and c Combination, where a, b, c can be single or multiple.
  • crystalline silicon cell is a high-efficiency crystalline silicon photovoltaic cell technology, and its cell efficiency (26.7%) is close to its theoretical limit efficiency (29.4%).
  • tandem cell technology has proved to be an effective way to break through the efficiency of traditional crystalline silicon photovoltaic cells.
  • Organic-inorganic hybrid perovskite solar cells have attracted worldwide attention as new high-efficiency and low-cost solar cells.
  • the photoelectric conversion efficiency of perovskite cells has rapidly climbed from 3.8% in 2009 to more than 25%, which is close to the efficiency of commercial silicon-based solar cells.
  • Perovskite cells can control the absorption spectral bandgap of perovskite cells in the range of 1.5eV-1.8eV by adjusting the composition formula, making perovskite cells an ideal tandem top cell.
  • the crystalline silicon-perovskite tandem cell which combines perovskite cells with crystalline silicon cells, is expected to achieve a photoelectric conversion efficiency of more than 30%.
  • some literatures have confirmed that the conversion efficiency of crystalline silicon-perovskite tandem cells can reach more than 25%.
  • the crystalline silicon-perovskite tandem cell uses the crystalline silicon cell as the bottom cell to absorb the energy of sunlight with a wavelength of 800nm-1200nm, and uses the perovskite cell as the top cell to absorb the energy of the sunlight with a wavelength of 300nm-800nm.
  • the bottom cell and the top cell are connected through the tunneling composite layer to form a two-terminal series cell, and the overall open circuit voltage of the stacked cell is the superposition of the voltages of the top cell and the bottom cell.
  • a tunnel junction is generally set between the top cell and the bottom cell to enhance the recombination of carriers.
  • the thickness of the tunnel junction, growth quality, impurity diffusion, etc. will have a great impact on the performance of the tunnel junction, and the preparation conditions are harsh.
  • organic materials are used for the hole transport layer of the top perovskite solar cell, the compatibility of the hole transport layer with the tunnel junction and the perovskite layer is poor, and it is difficult to form a perovskite film with better crystallinity, which affects the stacking. Fill factor and conversion efficiency of batteries.
  • the embodiments of the present application provide a stacked battery.
  • the stacked battery is not only suitable for the stacked battery with crystalline silicon battery as the bottom battery, but also for polycrystalline silicon battery, ingot monocrystalline silicon battery, copper indium gallium selenide battery, perovskite battery, gallium arsenide battery, organic Any of the photovoltaic cells is a tandem cell of a bottom cell, and is not limited thereto.
  • the stacked battery provided by the embodiment of the present application includes a stacked bottom battery 100 , a hole transport layer 310 , a perovskite absorption layer 320 , and a transparent conductive layer 340 .
  • the bottom battery 100 described above has a textured surface.
  • the bottom cell 100 may be any one of the bottom cells 100 described above, and is not limited thereto.
  • the suede surface may be a suede surface with a pyramid shape, or a suede surface with an inverted pyramid shape, or the like.
  • a passivation layer 210 may be formed on the bottom cell 100 .
  • the material of the passivation layer 210 may be silicon dioxide or the like. At this time, the passivation layer 210 can better passivate the bottom battery 100 and inhibit unfavorable carrier recombination. In practical applications, the passivation layer 210 can also be omitted.
  • the top layer of the bottom cell 100 is an n-type heavily doped layer 220 .
  • the n-type heavily doped layer 220 is located on the passivation layer 210 and is in contact with the hole transport layer 310 described below.
  • the n-type heavily doped layer 220 is in contact with the hole transport layer 310 to form a carrier recombination interface.
  • the bottom cell 100 may be an n-type cell or a p-type cell.
  • the n-type heavily doped layer 220, the passivation layer 210 below it, and the bottom cell 100 form a passivated cell structure, which can passivate the contact, reduce the unfavorable recombination of carriers, and improve the photovoltaic power of the bottom cell 100.
  • the n-type heavily doped layer may be a microcrystalline silicon layer doped with Group VA atoms such as phosphorus, arsenic, antimony, and bismuth.
  • the hole transport layer 310 is formed on the n-type heavily doped layer 220 , and the top energy level of the valence band of the hole transport layer 310 gradually decreases in the direction away from the bottom cell 100 .
  • the range of the top energy level of the valence band of the hole transport layer 310 is -4.5eV ⁇ -5.4eV.
  • the content of element B in the hole transport layer can be sequentially increased from the direction away from the perovskite absorber layer to the direction close to the perovskite absorber layer, and the top energy of the valence band of the hole transport layer level gradually decreases.
  • a hole transport layer with a gradually lower energy level at the top of the valence band can be fabricated by regulating the elements contained in the hole transport layer, and also by regulating the distribution and stoichiometry of the elements contained in the hole transport layer.
  • the specific elements of A, B and C in the semiconductor material AB ⁇ C x of the p-type delafossite structure, and the values of ⁇ and x can be selected according to the actual situation.
  • the distribution of the material can also be regulated during the fabrication process, so as to fabricate a hole transport layer with a gradually lower energy level at the top of the valence band.
  • each sub-layer uses p-type delafossite targets with different B contents
  • the first sub-layer uses a target with a composition of AB 0.9 O 2
  • the second sub-layer uses a target with composition ABO 2
  • the third sub-layer uses a target with composition AB 1.1 O 2 , wherein the first sub-layer is the first sub-layer in the direction away from the bottom cell, and the second sub-layer is the first sub-layer in the direction away from the bottom cell.
  • the sublayer is disposed on the first sublayer in the direction away from the bottom cell, and the third sublayer is disposed on the second sublayer in the direction away from the bottom cell, that is, the B element content of each sublayer varies from the direction away from the perovskite absorption layer to The direction of the absorber layer close to the perovskite increases sequentially.
  • the material of the hole transport layer 310 includes a semiconductor material with a p-type delafossite structure, the perovskite absorption layer 320 is formed on the hole transport layer 310, and the material of the perovskite absorption layer 320 is a semiconductor material with a perovskite structure .
  • its material includes a semiconductor material of p-type delafossite structure.
  • the energy levels between the three film layers are in a gradient relationship, so that the hole transport barrier can be reduced, the charge loss can be reduced, and the efficiency of the stacked battery can be improved. Hole transport properties and fill factor.
  • the top energy level of the valence band of the hole transport layer 310 gradually decreases.
  • the surface conduction band energy level is close to form a tunneling compound interface with the n-type heavily doped layer 220 on the bottom cell 100 , thereby omitting the tunneling compound layer of the tandem cell, simplifying the process of the tandem cell and reducing the difficulty of the process.
  • the energy band structure of the hole transport layer 310 is graded, which is beneficial to drive the transport of hole carriers.
  • the hole transport layer 310 made of the p-type delafossite structure semiconductor material and the n-type heavily doped layer 220 made of the inorganic material It has good compatibility and adaptability, and can improve various performance parameters and photoelectric conversion efficiency of tandem cells.
  • hole transport materials such as Spiro-OMeTAD or PTAA, which are expensive, complex to synthesize, and less stable after the introduction of dopants
  • p-type delafossite-structured semiconductor materials are mature and inexpensive, and can be easily fabricated. The manufacturing cost of the tandem battery is greatly reduced.
  • the above p-type delafossite structure semiconductor material is a high mobility p-type semiconductor material.
  • the general chemical formula of the p-type delafossite structure semiconductor material is AB ⁇ C x , wherein A is a monovalent soft acid cation, B is a trivalent cation, and C is an oxygen group element.
  • ⁇ is between 0.9-1.1 and x is between 1.95-2.6.
  • a may be 0.9, 1.0, 1.1; x may be 1.95, 2.0, 2.05, 2.1, 2.14, 2.3, 2.4, 2.5, or 2.6.
  • the general chemical formula of the semiconductor material with the perovskite structure is SDY 3 ; wherein, S is a monovalent organic cation, D is a divalent soft acid cation, and Y is a monovalent soft base anion.
  • the transport layer 310 can induce the crystalline growth of the perovskite material thereon, so as to easily form the perovskite absorption layer 320 with higher order and higher crystallinity, thereby improving the photoelectric conversion efficiency.
  • the soft acid cations of the p-type delafossite structure semiconductor material can interact with the Y ions (soft alkali ions) of the perovskite material.
  • the soft acid and soft base are coordinated, so that the interface defects of the perovskite absorption layer 320 can be passivated, the carrier recombination of the tandem battery can be reduced, and the photoelectric conversion efficiency can be improved.
  • the lattice matching of the contact interface between the hole transport layer 310 and the perovskite absorption layer 320 is high. , so that the hole extraction performance of the hole transport layer 310 can be improved.
  • a film with a higher degree of density can improve the performance of the perovskite absorption layer 320 to absorb sunlight and generate carriers, thereby improving the photoelectric conversion efficiency of the stacked battery.
  • A may include one or more of Cu + , Ag + , Pd + , Sr + , and Pt + , and often exists in a monovalent state.
  • B can include one or more of B 3+ , Al 3+ , Ga 3+ , In 3+ , Cr 3+ , Fe 3+ , Sc 3+ and trivalent rare earth cations, often in trivalent state, ⁇ is between 0.9-1.1.
  • C is an oxygen group element, including one or more of O, S, Se, and Te, and x is between 1.95 and 2.6.
  • the polarizability of these A ions is close to the polarizability of the Y ions in the perovskite material forming the perovskite absorption layer 320, so that they have a strong coordination force, which can further improve the empty space of the stacked battery. Hole transport capacity and photoelectric conversion efficiency.
  • the crystal structure space group of the semiconductor material of the p-type delafossite structure is R3m (space group No. 166).
  • R3m space group No. 166
  • C is O element and x is 2
  • one B atom can form BO 6 co-ordination with 6 O atoms
  • one A atom is respectively associated with phase
  • the two O atoms in the adjacent BO6 layer are linearly coordinated, and the A atoms form the A atomic layer.
  • the A atomic layer and the BO 6 layer form an alternating crystal structure and are stacked by OAO ionic bonds.
  • the ionic radius of the B atom can be in the changes within the range.
  • the p-type delafossite structure has a wide tolerance for B atoms, that is, B atoms have a wide selection space.
  • the optical, electrical and magnetic properties of p-type delafossite-structured semiconductor materials are different, so that p-type delafossite-structured semiconductor materials can achieve optical, electrical and optical properties in a wide range. and regulation of magnetic properties.
  • the band gap of the hole transport layer 310 can be adjusted in the range of 1.3eV-3.5eV through composition control.
  • the band gap of the hole transport layer 310 can be adjusted to be different from the band gap of the perovskite absorption layer 320 and the bottom cell 100, so as to prevent the hole transport layer 310 from absorbing solar energy in the absorbable band of the stack cell.
  • the band gap is 3.1eV
  • the top energy level of the valence band is -5.20eV
  • the bottom energy level of the conduction band is -2.10eV.
  • the top energy level of the valence band of AgGaO 2 is close to the HOMO energy level of the perovskite absorber layer 320 (about -5.30 eV), which is conducive to the collection of hole charges; on the other hand, the low energy level of its conduction band is far away from the perovskite.
  • the LUMO energy level of the absorption layer 320 (about -3.90 eV) can effectively block the diffusion of electrons.
  • the above hole transport layer 310 may be doped with metal or non-metal elements.
  • the metal can be Mg and the non-metal can be N.
  • the band gap width of the hole transport layer 310 can be adjusted by doping, so that the hole transport layer 310 can more easily match the energy levels of the n-type heavily doped layer 220 and the perovskite absorption layer 320 .
  • one or more of Mg, Ga, and Sr may be doped into the semiconductor material of the p-type delafossite structure for making the hole transport layer 310 .
  • a small change in the top energy level of the valence band of the hole transport layer 310 may occur.
  • the top energy level of the valence band of the hole transport layer 310 will decrease by 0.05 eV.
  • the above hole transport layer 310 may be formed on the n-type heavily doped layer 220 by a vacuum deposition process.
  • the thickness of the formed hole transport layer 310 is 5 nm to 100 nm.
  • the thickness of the hole transport layer 310 may be 5 nm, 18 nm, 20 nm, 30 nm, 40 nm, 47 nm, 50 nm, 60 nm, 70 nm, 77 nm, 85 nm, 90 nm, 95 nm, or 100 nm, or the like.
  • the contamination of impurities to the p-type delafossite-structured semiconductor material can be reduced, thereby forming high crystallinity, high purity, good compactness, combined with
  • the hole transport layer 310 with good strength can further improve the hole transport efficiency of the hole transport layer 310 and the combination performance with the n-type heavily doped layer 220, and increase the fill factor and photoelectric conversion efficiency of the tandem battery.
  • the perovskite absorber layer 320 may be fabricated by first co-evaporating to form a cation anchor layer, then spin-coating an anion salt and annealing.
  • the above-mentioned transparent conductive layer 340 is formed above the perovskite absorption layer 320 .
  • an electron transport layer 333 may also be included between the perovskite absorption layer 320 and the transparent conductive layer 340 , and an electrode 400 is further formed on the transparent conductive layer 340 and the bottom cell 100 .
  • Embodiments of the present application also provide a method for fabricating a laminated battery. Taking the fabrication of the n-type silicon heterojunction-perovskite tandem battery shown in FIG. 3 as an example, the fabrication method is as follows.
  • an n-type crystalline silicon wafer is provided.
  • a commercial grade M2 silicon wafer with a resistivity of 1 ⁇ .cm-10 ⁇ .cm and a thickness of 50 ⁇ m-200 ⁇ m can be selected.
  • the n-type crystalline silicon wafer is sequentially polished, textured and cleaned to form an n-type single crystal silicon substrate 101 with a textured surface.
  • an intrinsic amorphous silicon passivation layer is deposited on both sides of the n-type single crystal silicon substrate 101 to form a first passivation layer 102 located on the front side of the n-type single crystal silicon substrate 101 and located on the n-type single crystal silicon
  • the second passivation layer 103 on the backside of the substrate 101 .
  • the intrinsic amorphous silicon passivation layer may be fabricated by a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process or a catalytic chemical vapor deposition process.
  • the thickness of the intrinsic amorphous silicon passivation layer may be 1 nm-20 nm.
  • an n-type doped layer 104 is deposited on the first passivation layer 102 to form a front field structure.
  • the material of the n-type doped layer 104 is amorphous silicon or microcrystalline silicon.
  • the n-type doped layer 104 may be fabricated by a PECVD process, a hot wire chemical vapor deposition process or a catalytic chemical vapor deposition process.
  • the thickness of the n-type doped layer 104 may be 1 nm-30 nm.
  • a p-type doped layer 105 is deposited on the second passivation layer 103 to form a backside emitter.
  • the material of the p-type doped layer is amorphous silicon or microcrystalline silicon.
  • the p-type doped layer 105 may be fabricated by using a PECVD process, a hot wire chemical vapor deposition process or a catalytic chemical vapor deposition process.
  • the thickness of the p-type doped layer 105 may be 1 nm-30 nm.
  • a first transparent conductive layer 106 is formed on the p-type doped layer 105 to realize collection and transmission of photo-generated carriers.
  • the first transparent conductive layer 106 may be fabricated by a magnetron sputtering process.
  • the material of the first transparent conductive layer 106 may be indium tin oxide (ITO), tungsten-doped indium oxide (In 2 O 3 :W, abbreviated as IWO), indium zinc oxide (IZO), titanium-doped indium oxide thin ( one or more of ITiO).
  • the thickness of the first transparent conductive layer 106 may be 30nm-120nm.
  • the resulting structure is defined as the bottom cell 100, which has a textured surface.
  • the battery may be fabricated by providing an n-type crystalline silicon wafer as the process starting point, or the stacked battery may be fabricated with the bottom cell 100 defined in this application as the process starting point.
  • a passivation layer 210 is formed on the n-type doped layer 104 to realize contact passivation.
  • the passivation layer 210 may be fabricated by a magnetron sputtering process, chemical vapor deposition or other processes.
  • an n-type heavily doped layer 220 is formed on the silicon passivation layer 210 .
  • the surface of the n-type heavily doped layer and the below-mentioned hole transport layer 310 close to the bottom cell 100 forms a tunneling recombination interface to realize the tunneling recombination collection of photogenerated carriers.
  • the n-type heavily doped layer 220 may be a phosphorus-doped microcrystalline silicon thin film.
  • the n-type heavily doped layer 220 can be fabricated by PECVD process, hot wire chemical vapor deposition process or catalytic chemical vapor deposition process.
  • a p-type delafossite structure semiconductor material hole transport layer 310 is formed on the n-type heavily doped layer 220 .
  • the top energy level of the valence band of the hole transport layer 310 gradually decreases, and the range of the top energy level of the valence band is -4.5eV ⁇ -5.4eV.
  • the hole transport layer 310 may be fabricated by a vacuum deposition process.
  • the vacuum deposition process may be a magnetron sputtering process, a laser pulse deposition process or a thermal evaporation coating process.
  • the hole transport layer 310 is fabricated by a magnetron sputtering process, a hole transport layer with a thickness of 5 nm-100 nm is formed.
  • a perovskite absorber layer 320 is formed on the hole transport layer 310 . Specifically include:
  • Lead iodide and cesium bromide are formed on the hole transport layer 310 by a co-evaporation method, with a total thickness of 250nm-1000nm.
  • the mixed solution of formamidine hydroiodide (FAI) and formamidine hydrobromide (FABr) is coated on lead iodide and cesium bromide, and the mixed solution of FAI and FABr reacts with lead iodide and cesium bromide.
  • a thin film of perovskite material is formed.
  • the molar concentration ratio of FAI and FABr can be (2-4):1, and the solvent of the mixed solution of FAI and FABr can be ethanol or isopropanol.
  • the perovskite material thin film is annealed to form the perovskite absorption layer 320 .
  • the annealing temperature may be 100°C-200°C
  • the annealing time may be 5min-30min
  • the thickness of the perovskite absorption layer 320 may be 100nm-1000nm.
  • the material composition of the perovskite absorption layer 320 is Cs x FA 1-x Pb(Br y I 1-y ) 3 .
  • the perovskite absorption layer 320 is fabricated by the above method, since the cationic salt rapidly reacts with the underlying lead iodide to form a perovskite film, the excess unreacted cationic salt solution is thrown away from the processing interface during the spin coating process, thereby avoiding accumulation in Pyramid-shaped suede valley bottom, therefore, a uniform perovskite film can be conformally deposited on the suede surface.
  • an electron transport interface layer 331 and a leakage repair layer 332 are sequentially formed on the perovskite absorption layer 320 .
  • the electron transport interface layer 331 can be a LiF thin film layer
  • the leakage repair layer 332 can be a C60, fullerene derivative (PCBM) thin film layer.
  • the LiF thin film layer and the C60 thin film layer can be fabricated by thermal evaporation
  • the thickness of the electron transport interface layer 331 can be 0.1 nm-10 nm
  • the thickness of the leakage repair layer 332 can be 1 nm-20 nm.
  • one of the electron transport interface layer 331 and the leakage repair layer 332 may be omitted, or all of them may be omitted.
  • the electron transport layer 333 is formed on the electron transport interface layer 331 .
  • the material of the electron transport layer 333 can be SnO 2
  • the layer thickness can be 1 nm-30 nm
  • the manufacturing process can be atomic layer deposition (ALD), chemical vapor deposition, physical vapor deposition, solution coating process any of the.
  • a second transparent conductive layer 341 is formed on the electron transport layer 333 to collect photo-generated carriers.
  • the material, thickness and formation process of the second transparent conductive layer 341 may refer to the first transparent conductive layer 106 .
  • electrodes 400 are formed on the first transparent conductive layer 106 and the second transparent conductive layer 341 to collect current.
  • the grid lines of the electrodes 400 may be fabricated by screen printing or mask evaporation.
  • the thickness of the electrode 400 may be 100 nm-500 nm, and the material of the electrode 400 may be a metal with good electrical conductivity such as silver, copper, and aluminum.
  • Figure 17a shows a schematic front view of an n-type silicon heterojunction-perovskite tandem cell
  • Figure 17b shows a schematic diagram of the back side of an n-type silicon heterojunction-perovskite stack.
  • the electrode 400 is formed on the first transparent conductive layer 106 and the second transparent conductive layer 341 .
  • the first step is to provide an n-type M2 silicon wafer with a resistivity of 4 ⁇ .cm and a thickness of 180 ⁇ m.
  • the silicon wafer is polished, textured and cleaned to form an n-type single crystal silicon substrate with textured surfaces.
  • the second step is to use PECVD equipment to deposit intrinsic amorphous silicon passivation layers (thickness 5nm) on both sides of the n-type single crystal silicon substrate to form a first passivation layer on the front side of the n-type single crystal silicon substrate, which is located on the n-type single crystal silicon substrate.
  • the second passivation layer on the backside of the crystalline silicon substrate.
  • the third step is to deposit an N-type amorphous silicon layer (thickness 10 nm) doped with phosphorus (doping concentration 10 20 cm - 3 ) on the first passivation layer using PECVD equipment to form a front field structure.
  • a P-type amorphous silicon layer (thickness 10 nm) doped with boron (doping concentration 10 19 cm - 3 ) is deposited on the second passivation layer of the PECVD equipment to form a back field emitter.
  • a first transparent conductive layer (thickness 100 nm) of ITO material is prepared on the P-type amorphous silicon layer by a magnetron sputtering process.
  • a passivation layer is formed on the n-type amorphous silicon layer by a magnetron sputtering process.
  • a phosphorus-doped n-type heavily doped layer is formed on the passivation layer by using PECVD equipment.
  • a hole transport layer made of AgGax O 2 is fabricated on the n-type heavily doped layer by a magnetron sputtering process.
  • Three-layer composite hole transport material is prepared by using three AgGa x O 2 targets with different compositions. Specifically, the first layer adopts a target with a composition of AgGa 0.9 O 2 , and the second layer adopts a target with a composition of AgGaO 2 The third layer uses a target with a composition of AgGa 1.1 O 2 .
  • the thickness of each hole transport layer is 5nm, and the total thickness of the hole transport layer is 15nm.
  • lead iodide and cesium bromide are formed on the hole transport layer by a co-evaporation method, with a total thickness of 350 nm.
  • a mixed solution of FAI and FABr was prepared, the molar concentration ratio of FAI and FABr was 3:1, and the solvent was ethanol. 100 ⁇ L of mixed solution of FAI and FABr was spin-coated on the lead iodide and cesium bromide layers and reacted to form a perovskite material film.
  • the perovskite material film was annealed for 30min to form a dense and uniform perovskite absorber layer (thickness 500nm), the absorber layer material composition was Cs x FA 1-x Pb(BryI 1-y ) 3 .
  • the tenth step is to form a LiF thin film layer (thickness 1 nm) and a C60 thin film layer (thickness 10 nm) on the perovskite absorber layer by thermal evaporation process.
  • the eleventh step is to use an atomic layer deposition (ALD) process to fabricate an electron transport layer made of SnO 2 (thickness 10 nm).
  • ALD atomic layer deposition
  • a second transparent conductive layer (thickness 100 nm) made of ITO material is formed on the electron transport layer by a magnetron sputtering process.
  • silver electrode grid lines are formed on the first transparent conductive layer and the second transparent conductive layer by a screen printing process.
  • the first step is to provide an n-type silicon wafer with a resistivity of 1 ⁇ .cm and a thickness of 50 ⁇ m.
  • the silicon wafer is polished, textured and cleaned to form an n-type single crystal silicon substrate with textured surfaces.
  • the second step use PECVD equipment to deposit intrinsic amorphous silicon passivation layers (thickness 1nm) on both sides of the n-type single crystal silicon substrate to form a first passivation layer on the front side of the n-type single crystal silicon substrate, which is located on the n-type single crystal silicon substrate.
  • the second passivation layer on the backside of the crystalline silicon substrate.
  • an N-type amorphous silicon layer (thickness 1 nm) doped with phosphorus (doping concentration 10 20 cm - 3 ) is deposited on the first passivation layer using PECVD equipment to form a front field structure.
  • a P-type amorphous silicon layer (thickness 1 nm) doped with boron (doping concentration 10 19 cm - 3 ) is deposited on the second passivation layer of the PECVD equipment to form a back field emitter.
  • a first transparent conductive layer (thickness 30 nm) made of ITO material is prepared on the P-type amorphous silicon layer by a magnetron sputtering process.
  • a passivation layer is formed on the n-type amorphous silicon layer by a magnetron sputtering process.
  • a phosphorus-doped n-type heavily doped layer is formed on the passivation layer by using PECVD equipment.
  • a hole transport layer made of AgCr x O 2 is fabricated on the n-type heavily doped layer by a laser pulse deposition process.
  • Three-layer composite hole transport materials are prepared by using three AgCr x O 2 targets with different compositions. Specifically, the first layer uses a target with a composition of AgCr 0.95 O 2 , and the second layer uses a target with a composition of AgCrO 2 The third layer uses a target with a composition of AgCr 1.05 O 2 .
  • the thickness of each hole transport layer is 5nm, and the total thickness of the hole transport layer is 15nm. In the direction away from the bottom cell, the top energy level of the valence band of the hole transport layer gradually decreases, and the range of the top energy level of the valence band is -4.5eV ⁇ -5.4eV.
  • lead iodide and cesium bromide are formed on the hole transport layer by a co-evaporation method, with a total thickness of 250 nm.
  • a mixed solution of FAI and FABr was prepared, the molar concentration ratio of FAI and FABr was 2:1, and the solvent was ethanol. 100 ⁇ L of mixed solution of FAI and FABr was spin-coated on the lead iodide and cesium bromide layers and reacted to form a perovskite material film.
  • the perovskite material film was annealed for 5 minutes to form a dense and uniform perovskite absorber layer (thickness 100nm), and the absorber layer material composition was Cs x FA 1-x Pb(BryI 1-y ) 3 .
  • a LiF thin film layer (thickness 0.1 nm) and a C60 thin film layer (thickness 1 nm) are formed on the perovskite absorber layer by a thermal evaporation process.
  • the eleventh step is to use an atomic layer deposition (ALD) process to fabricate an electron transport layer (thickness 1 nm) made of SnO 2 .
  • ALD atomic layer deposition
  • a second transparent conductive layer (thickness 30 nm) made of ITO material is formed on the electron transport layer by a magnetron sputtering process.
  • silver electrode grid lines are formed on the first transparent conductive layer and the second transparent conductive layer by a screen printing process.
  • the first step is to provide an n-type silicon wafer with a resistivity of 10 ⁇ .cm and a thickness of 200 ⁇ m.
  • the silicon wafer is polished, textured and cleaned to form an n-type single crystal silicon substrate with textured surfaces.
  • the second step is to use PECVD equipment to deposit intrinsic amorphous silicon passivation layers (thickness 20nm) on both sides of the n-type single crystal silicon substrate to form a first passivation layer on the front side of the n-type single crystal silicon substrate, which is located on the n-type single crystal silicon substrate.
  • the second passivation layer on the backside of the crystalline silicon substrate.
  • the third step is to deposit an N-type amorphous silicon layer (thickness 30nm) doped with phosphorus (doping concentration 10 20 cm - 3 ) on the first passivation layer by using PECVD equipment to form a front field structure.
  • a P-type amorphous silicon layer (thickness 30nm) doped with boron (doping concentration 10 19 cm - 3 ) is deposited on the second passivation layer of the PECVD equipment to form a back field emitter.
  • a first transparent conductive layer (thickness 120 nm) of ITO material is prepared on the P-type amorphous silicon layer by a magnetron sputtering process.
  • a passivation layer is formed on the n-type amorphous silicon layer by a magnetron sputtering process.
  • a phosphorus-doped n-type heavily doped layer is formed on the passivation layer by using PECVD equipment.
  • a hole transport layer made of AgGa x O 2 is fabricated on the n-type heavily doped layer by a laser pulse deposition process.
  • Three-layer composite hole transport materials are prepared by using three AgGa x O 2 targets with different compositions. Specifically, the first layer uses a target with a composition of AgGa 0.95 O 2 , and the second layer uses a target with a composition of AgGaO 2 The third layer uses a target with a composition of AgGa 1.05 O 2 .
  • the thickness of each hole transport layer is 25nm, and the total thickness of the hole transport layer is 75nm. In the direction away from the bottom cell, the top energy level of the valence band of the hole transport layer gradually decreases, and the range of the top energy level of the valence band is -4.5eV ⁇ -5.4eV.
  • lead iodide and cesium bromide are formed on the hole transport layer by a co-evaporation method, with a total thickness of 1000 nm.
  • a mixed solution of FAI and FABr was prepared, the molar concentration ratio of FAI and FABr was 4:1, and the solvent was ethanol. 100 ⁇ L of mixed solution of FAI and FABr was spin-coated on the lead iodide and cesium bromide layers and reacted to form a perovskite material film.
  • the perovskite material film was annealed for 30 minutes to form a dense and uniform perovskite absorber layer (thickness 1000nm), and the absorber layer material composition was Cs x FA 1-x Pb(BryI 1-y ) 3 .
  • a LiF thin film layer (thickness 10 nm) and a C60 thin film layer (thickness 20 nm) are formed on the perovskite absorber layer by a thermal evaporation process.
  • the eleventh step is to use an atomic layer deposition (ALD) process to fabricate an electron transport layer made of SnO 2 (thickness 30nm).
  • ALD atomic layer deposition
  • a second transparent conductive layer (thickness 120 nm) made of ITO material is formed on the electron transport layer by a magnetron sputtering process.
  • silver electrode grid lines are formed on the first transparent conductive layer and the second transparent conductive layer by a screen printing process.
  • the manufacturing method of the laminated battery provided in this comparative example is basically the same as the method described in the above-mentioned embodiment 1, except that the material of the hole transport layer is Spiro-TTB, and the preparation process of the hole transport layer is a thermal evaporation process.
  • the top energy level of the valence band is the same everywhere in the hole transport layer, and there is a p-type heavily doped layer between the passivation layer and the hole transport layer.
  • the manufacturing method of the laminated battery provided in this comparative example is basically the same as the method described in the above-mentioned first embodiment, the only difference is that the material of the hole transport layer is nickel oxide.
  • the top energy level of the valence band is the same everywhere in the hole transport layer, and there is a p-type heavily doped layer between the passivation layer and the hole transport layer.
  • FIG. 18 shows the SEM image of the surface morphology of the stacked battery prepared in Example 1.
  • FIG. 19 shows the SEM image of the cross-section of the laminated battery prepared in Example 1.
  • FIG. 18 It can be seen from FIG. 18 that the surface of the laminated battery prepared in Example 1 is a pyramid textured surface. It can be seen from Fig. 19 that the lower surface of the perovskite absorber layer is in close contact with the hole transport layer, and no defects at the pyramid tips or accumulation of valley bottoms between the towers are observed.
  • each functional layer of the top battery of the stacked battery prepared in Example 1 can be distributed along the pyramid texture of the bottom battery, and the interface between the hole transport layer and the perovskite absorption layer is in good contact, and the perovskite absorbs The quality of the film formation is good.
  • FIG. 20 shows the IV curves of the tandem cells prepared in Example 1, Comparative Example 1 and Comparative Example 2 under the strong irradiation of AM1.5G sunlight. It can be seen from Figure 20 that the short-circuit current J sc of the laminated battery prepared in Example 1 is 20.2 mA/cm 2 , the open-circuit voltage V oc is 1.69 V, the filling factor FF is 77%, and the final battery conversion efficiency is 26.3%.
  • FIG. 21 shows the schematic diagrams of the energy bands of the stacked batteries provided by Comparative Example 1 and Comparative Example 2;
  • FIG. 22 shows the schematic diagrams of the energy bands of the stacked batteries of Examples 1 to 3. Comparing FIG. 21 and FIG.
  • the valence band top of the hole transport layer The energy level is relatively close to the valence band energy level of the perovskite absorption layer, and the low conduction band energy level of the hole transport layer is close to the conduction band energy level of the n-type heavily doped layer, which makes the contact barrier smaller and can improve the hole transport efficiency. , and the carrier recombination efficiency is high.
  • Example 1 The device performance parameters of the stacked battery prepared in Example 1 are obviously better than those of the traditional stacked battery. Table 1 shows the performance parameters of the laminated batteries prepared in each example and comparative example.
  • the short-circuit current J sc of the laminated battery prepared in Example 1 is 20.2 mA/cm 2
  • the open-circuit voltage V oc is 1.69 V
  • the filling factor FF is 77%
  • the final battery conversion efficiency is 26.3% .
  • the device performance parameters of the laminated battery prepared in Example 1 are obviously better than those of the traditional laminated batteries in Comparative Example 1 and Comparative Example 2. Comparing Example 1 and Example 2, it can be seen that by adjusting the material of the hole transport layer, the fill factor of the stacked battery can be finely regulated. Comparing Example 1 and Example 3, it can be seen that better performance of the stacked battery can be obtained by using different vacuum deposition processes.

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Abstract

本申请公开一种叠层电池及其制作方法，涉及光伏技术领域，以提高叠层电池的空穴传输性能。该叠层电池包括底电池、形成在底电池上的空穴传输层、形成在空穴传输层上的钙钛矿吸收层以及形成在钙钛矿吸收层上方的透明导电层。空穴传输层的材料包括p型铜铁矿结构的半导体材料，在背离底电池的方向上，空穴传输层的价带顶能级逐渐降低，兼具载流子传输和载流子复合双重功能，以实现简化的电池结构和优化光电转换效率的功能。本申请提供的叠层电池及其制作方法用于叠层电池的生产制造。

Description

一种叠层电池及其制作方法
相关申请的交叉引用
本公开要求在2020年10月9日提交中国专利局、申请号为202011073513.7、名称为“一种叠层电池及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本申请涉及光伏技术领域，尤其涉及一种叠层电池及其制作方法。
背景技术
有机-无机杂化钙钛矿太阳能电池作为新型高效率、低成本太阳能电池在全世界范围内被广泛关注。短短几年时间里，钙钛矿电池的光电转换效率从2009年的3.8％迅速攀升到超过25％以上，已接近商业化硅基太阳能电池的效率。
为了进一步提高光伏电池转换效率，可以将多个不同带隙的太阳能电池通过隧穿复合层串联起来。钙钛矿太阳能电池具有较宽的带隙，可以作为叠层电池的顶电池。当钙钛矿太阳能电池与具有绒面结构的底电池层叠在一起时，如何提高空穴传输层的空穴传输性能，进而提高叠层电池的填充因子和转换效率，成为叠层电池的一个重点。
发明内容
本申请的目的在于提供一种叠层电池，以提高叠层电池的空穴传输性能。
第一方面，本申请提供一种叠层电池。该叠层电池包括底电池、形成在底电池上的空穴传输层、形成在空穴传输层上的钙钛矿吸收层以及形成在钙钛矿吸收层上方的透明导电层。该空穴传输层的材料包括p型铜铁矿结构的半导体材料，在背离底电池的方向上，空穴传输层的价带顶能级逐渐降低。
采用上述技术方案时，形成在底电池上的空穴传输层，其材料包括p型铜铁矿结构的半导体材料。与此同时，在背离底电池的方向上，空穴传输层的 价带顶能级逐渐降低，此时，空穴传输层靠近底电池的表面价带顶能级与底电池表面导带能级较接近，可以替代隧穿复合层的p型重掺杂层与底电池上的n型重掺杂层构成隧穿复合界面，从而省略叠层电池的隧穿复合层，简化叠层电池的工艺，降低工艺难度，且和隧穿复合层的结构相比，减少了空穴传输层和隧穿复合层的接触界面，减少了载流子的界面复合。此外，空穴传输层的梯度能级有利于空穴载流子的传输，从而提高了太阳能电池的光电转换效率。
在一些可能的实现方式中，上述p型铜铁矿结构的半导体材料的化学通式为AB αC x，包括Cu +、Ag +、Pd +、Sr +、Pt +中的一种或多种，B包括B 3+、Al 3+、Ga 3+、In 3+、Cr 3+、Fe 3+、Sc 3+及三价稀土阳离子中的一种或多种，α在0.9-1.1之间，C为氧族元素，包括O、S、Se、Te中的一种或多种，x在1.95-2.6之间，α在0.9-1.1之间。
采用上述技术方案时，上述A离子的可极化程度与形成钙钛矿吸收层的钙钛矿材料中的卤素离子的可极化性较接近，从而具有较强的配位作用力，能够降低空穴传输层与钙钛矿吸收层之间的界面接触缺陷，提高界面接触性能，进而提高叠层电池的空穴传输能力和光电转换效率。
在一些可能的实现方式中，上述空穴传输层中B元素的含量从背离所述钙钛矿吸收层到靠近所述钙钛矿的吸收层的方向上依次增加，空穴传输层的价带顶能级逐渐降低。
在一些可能的实现方式中，上述空穴传输层的厚度为5nm～100nm。
在一些可能的实现方式中，上述空穴传输层的价带顶能级变化范围为-4.5eV～-5.4eV。
在一些可能的实现方式中，上述底电池的顶层为n型重掺杂层。n型重掺杂层与空穴传输层接触而形成载流子复合界面。该底电池可以为n型电池或p型电池。此时，一方面，n型重掺杂层与其下方的钝化层、底电池构成钝化电池结构，可以钝化接触，降低载流子的不利复合，提高底电池的光电转换效率；另一方面，n型重掺杂层与空穴传输层靠近底电池的表面构成隧穿复合界面，实现底电池和顶电池之间载流子的隧穿复合。
在一些可能的实现方式中，上述叠层电池还包括位于底电池和n型重掺杂层之间的钝化层。此时，钝化层能够起到较好的钝化底电池的作用，抑制不利的载流子复合。
在一些可能的实现方式中，上述底电池为晶体硅底电池、多晶硅底电池、铸锭单晶硅底电池、铜铟镓硒底电池、钙钛矿底电池、砷化镓底电池、有机光伏底电池中的任一种。
采用上述技术方案时，由于空穴传输层和钙钛矿吸收层均具有可调整的带隙，因此，可以与上述的多种底电池电流匹配，从而获得高转换效率的叠层电池。
第二方面，本申请还提供一种上述叠层电池的制作方法。该叠层电池的制作方法包括：
提供一底电池；
采用真空沉积工艺在底电池上形成空穴传输层，空穴传输层的材料包括p型铜铁矿结构的半导体材料，在背离底电池的方向上，空穴传输层的价带顶能级逐渐降低；
在空穴传输层上形成钙钛矿吸收层；
在钙钛矿吸收层上形成电子传输层和透明导电层。
在一些可能的实现方式中，上述真空沉积工艺为磁控溅射工艺、激光脉冲沉积工艺或热蒸发镀膜工艺。
在一些可能的实现方式中，在空穴传输层上形成钙钛矿吸收层包括：
采用共蒸法在空穴传输层上形成碘化铅和溴化铯；
在碘化铅和溴化铯上涂布甲脒氢碘酸盐及甲脒氢溴酸盐混合溶液，形成钙钛矿材料薄膜；
对钙钛矿材料薄膜进行退火处理，形成钙钛矿吸收层。
第二方面或第二方面任一可能的实现方式所提供的叠层电池的制作方法的有益效果，可以参考第一方面或第一方面任一可能的实现方式所描述的叠层电池的有益效果，在此不做赘述。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本申请实施例提供的叠层电池结构示意图；
图2a和图2b为本申请实施例中p型铜铁矿结构的半导体材料晶体结构示意图，其中，a为p型铜铁矿结构的半导体材料的晶体结构一，b为p型铜铁矿结构的半导体材料的晶体结构二；
图3为本申请实施例提供的一种n型硅异质结-钙钛矿叠层电池结构示意图；
图4至图16为本申请实施例提供的n型硅异质结-钙钛矿叠层电池的制作过程的各个阶段状态示意图；
图17a为图3所示的n型硅异质结-钙钛矿叠层电池正面示意图；
图17b为图3所示的n型硅异质结-钙钛矿叠层电池背面正面示意图；
图18为本申请实施例一所制备的叠层电池的表面形貌SEM图；
图19为本申请实施例一所制备的叠层电池截面SEM图；
图20为本申请实施例一、对比例一及对比例二所制备的叠层电池的I-V曲线；
图21为对比一和对比例二提供的叠层电池能带示意图；
图22为本申请实施例提供的叠层电池的能带示意图。
附图标记：
100-底电池，101-n型单晶硅基底，102-第一钝化层，103-第二钝化层，104-n型掺杂层，105-p型掺杂层，106-第一透明导电层，210-钝化层，220-n型重掺杂层，310-空穴传输层，320-钙钛矿吸收层，331-电子传输界面层，332-漏电修复层，333-电子传输层，340-透明导电层，341-第二透明导电层，400-电极。
具体实施例
为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特 定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b的结合，a和c的结合，b和c的结合，或a、b和c的结合，其中a，b，c可以是单个，也可以是多个。
目前，晶体硅电池作为光伏领域的主流产品，是一种高效率晶硅光伏电池技术，其电池效率(26.7％)已经接近其理论极限效率(29.4％)。随着光伏技术的不断发展，叠层电池技术被证实是突破传统晶硅光伏电池效率的有效途径。
有机-无机杂化钙钛矿太阳能电池作为新型高效率、低成本太阳能电池在全世界范围内被广泛关注。短短几年时间里，钙钛矿电池的光电转换效率从2009年的3.8％迅速攀升到超过25％以上，已接近商业化硅基太阳能电池的效率。钙钛矿电池可以通过调整组份配方在1.5eV-1.8eV范围内调控钙钛矿电池的吸收光谱带隙，使得钙钛矿电池可以成为理想的叠层顶电池。钙钛矿电池与晶体硅电池结合的晶体硅-钙钛矿叠层电池，有望实现30％以上的光电转换效率。目前，有文献证实晶体硅-钙钛矿叠层电池转换效率可以达到25％以上。
晶体硅-钙钛矿叠层电池以晶体硅电池作为底电池吸收800nm-1200nm波长的太阳光的能量，以钙钛矿电池作为顶电池吸收300nm-800nm波长的太阳光的能量。底电池与顶电池通过隧穿复合层连接形成两端串联电池，叠层电池的整体开路电压为顶电池和底电池的电压叠加。
底电池与顶电池之间的内部串联需要同时满足降低光学吸收和欧姆接触两个条件，现有技术中一般在顶电池和底电池之间设置隧穿结来增强载流子 的复合，但隧穿结的厚度、生长质量、杂质扩散等都会对隧穿结性能有极大影响，制备条件苛刻。此外，顶层钙钛矿太阳能电池的空穴传输层采用有机材料时，空穴传输层和隧道结以及钙钛矿层的兼容性较差，不易形成结晶度较好的钙钛矿薄膜，影响叠层电池的填充因子和转换效率。
为了解决上述技术问题，本申请实施例提供一种叠层电池。该叠层电池不仅适用于以晶体硅电池为底电池的叠层电池，也适用于以多晶硅电池、铸锭单晶硅电池、铜铟镓硒电池、钙钛矿电池、砷化镓电池、有机光伏电池中的任一种为底电池的叠层电池，且不仅限于此。
如图1所示，本申请实施例提供的叠层电池包括层叠的底电池100、空穴传输层310、钙钛矿吸收层320以及透明导电层340。
上述底电池100具有绒面。该底电池100可以为上述底电池100中的任一种，且不仅限于此。该绒面可以是金字塔形貌的绒面，也可以是倒金字塔形貌的绒面等。
上述底电池100上可以形成有钝化层210。钝化层210的材料可以为二氧化硅等。此时，钝化层210能够起到较好的钝化底电池100的作用，抑制不利的载流子复合。在实际应用中，钝化层210也可以省略。
上述底电池100的顶层为n型重掺杂层220，n型重掺杂层220位于钝化层210上，并与下述的空穴传输层310接触。n型重掺杂层220与空穴传输层310接触而形成载流子复合界面。底电池100可以为n型电池，也可以为p型电池。此时，一方面，n型重掺杂层220与其下方的钝化层210、底电池100构成钝化的电池结构，可以钝化接触，降低载流子的不利复合，提高底电池100的光电转换效率；另一方面，n型重掺杂层220与空穴传输层310靠近底电池100的表面构成隧穿复合界面，实现底电池100和顶电池之间载流子的隧穿复合。具体的，n型重掺杂层可以为掺杂有磷、砷、锑、铋等第ⅤA族原子的微晶硅层。
上述空穴传输层310形成在n型重掺杂层220上，在背离底电池100的方向上，空穴传输层310的价带顶能级逐渐降低。空穴传输层310的价带顶能级变化范围为-4.5eV～-5.4eV。
在实际应用中，可以使空穴传输层中B元素的含量从背离所述钙钛矿吸收层到靠近所述钙钛矿的吸收层的方向上依次增加，空穴传输层的价带顶能 级逐渐降低。
具体的，可以通过调控空穴传输层所含有的元素，也可以调控空穴传输层所含有的元素的分布，以及化学配比，从而制作价带顶能级逐渐降低的空穴传输层。
例如，制作空穴传输层时，可以根据实际情况选择p型铜铁矿结构的半导体材料AB αC x中A、B及C具体为何种元素，以及α和x的数值。当然，也可以在制作过程中，调控材料的分布情况，从而制作价带顶能级逐渐降低的空穴传输层。
具体的，通过溅射沉积三个子层p型铜铁矿薄膜，每一子层使用含有不同B含量的p型铜铁矿靶材，例如，第一子层使用组成为AB 0.9O 2的靶材，第二子层使用组成为ABO 2的靶材，第三子层使用组成为AB 1.1O 2的靶材，其中，第一子层为背离底电池方向上的第一子层，第二子层背离底电池方向设置在第一子层上，第三子层为背离底电池方向上设置在第二子层上，也就是各子层B元素含量从背离所述钙钛矿吸收层到靠近所述钙钛矿的吸收层的方向上依次增加。
空穴传输层310的材料包括p型铜铁矿结构的半导体材料，上述钙钛矿吸收层320形成在空穴传输层310上，钙钛矿吸收层320的材料为钙钛矿结构的半导体材料。
鉴于形成在底电池100上的空穴传输层310，其材料包括p型铜铁矿结构的半导体材料。此时，从钙钛矿吸收层320、空穴传输层310到底电池100，三个膜层间能级为递变关系，从而可以降低空穴传输壁垒，降低电荷损耗，进而提高叠层电池的空穴传输性能和填充因子。
与此同时，在背离底电池100的方向上，空穴传输层310的价带顶能级逐渐降低，此时，空穴传输层310靠近底电池100的表面价带顶能级与底电池100表面导带能级接近，可以与底电池100上的n型重掺杂层220形成隧穿复合界面，从而省略叠层电池的隧穿复合层，简化叠层电池的工艺，降低工艺难度。另外，空穴传输层310的能带结构渐变，有利于驱动空穴载流子的传输。
此外，由于p型铜铁矿结构的半导体材料是一种无机半导体材料，因此，p型铜铁矿结构的半导体材料制成的空穴传输层310和无机材料制备的n型 重掺杂层220具有良好的兼容性和适配性，可以提高叠层电池的各项性能参数及光电转换效率。并且，与Spiro-OMeTAD或PTAA等价格昂贵、合成复杂且引入掺杂剂后稳定性较差的空穴传输材料相比，p型铜铁矿结构的半导体材料制作方法成熟，且价格低廉，可以大大降低叠层电池的制作成本。
上述p型铜铁矿结构的半导体材料是一种高迁移率的p型半导体材料。该p型铜铁矿结构的半导体材料的化学通式为AB αC x，其中，A为一价软酸阳离子，B为三价阳离子，C为氧族元素。其中α在0.9-1.1之间，x在1.95-2.6之间。例如，α可以为0.9、1.0、1.1；x可以为1.95、2.0、2.05、2.1、2.14、2.3、2.4、2.5或2.6。上述钙钛矿结构的半导体材料的化学通式为SDY 3；其中，S为一价有机阳离子，D为二价软酸阳离子，Y为一价软碱阴离子。
根据软酸软碱容易稳定结合的原理，一方面，钙钛矿吸收层320含有的Y离子与空穴传输层310含有的A离子之间存在较强的相互作用力，使得含有A离子的空穴传输层310能够在其上诱导钙钛矿材料结晶生长，进而容易形成有序度较高、结晶度较高的钙钛矿吸收层320，提高光电转换效率。与此同时，在空穴传输层310与钙钛矿吸收层320的界面处，p型铜铁矿结构的半导体材料的软酸阳离子，可以与钙钛矿材料的Y离子(软碱离子)进行软酸软碱配位，从而可以钝化钙钛矿吸收层320的界面缺陷，减少叠层电池的载流子复合，提高光电转换效率。另外，由于A离子与钙钛矿吸收层320中的Y离子之间的软酸软碱配位作用力，使得空穴传输层310与钙钛矿吸收层320之间的接触界面晶格匹配度高，从而可以提高空穴传输层310的空穴抽取性能。另一方面，钙钛矿吸收层320含有的Y离子与软酸阳离子D之间，也存在较强的相互作用力，可以进行软酸软碱配位，从而可以依靠两者间的作用力形成结晶度较高的薄膜，提高钙钛矿吸收层320吸收太阳光、生成载流子的性能，进而提高叠层电池的光电转换效率。
上述p型铜铁矿结构的半导体材料中，A可以包括Cu +、Ag +、Pd +、Sr +、Pt +中的一种或多种，常常以一价态存在。B可以包括B 3+、Al 3+、Ga 3+、In 3+、Cr 3+、Fe 3+、Sc 3+及三价稀土阳离子中的一种或多种，常常以三价态存在，α在0.9-1.1之间。C为氧族元素，包括O、S、Se、Te中的一种或多种，x在1.95-2.6之间。这些A离子的极化程度与形成钙钛矿吸收层320的钙钛矿材料中的Y离子的可极化性较接近，从而具有较强的配位作用力，可以进一步提高叠层 电池的空穴传输能力和光电转换效率。
p型铜铁矿结构的半导体材料的晶体结构空间群为R3m(空间群NO.166)。如图2a和图2b所示，当C为O元素，x为2时，在其晶体结构中，一个B原子可以与6个O原子形成BO 6共棱八配位，一个A原子分别与相邻BO 6层中的两个O原子线性配位，且A原子形成A原子层。A原子层与BO 6层形成交替晶体结构并通过O-A-O离子键层叠。在八配位BO 6结构中，B原子的离子半径可以在
Figure PCTCN2021122897-appb-000001
的范围内变化。可见，p型铜铁矿结构对于B原子具有宽泛的容忍度，即B原子具有较宽泛的选择空间。鉴于B原子的离子半径不同，会导致p型铜铁矿结构的半导体材料的光学、电学和磁学性质不同，使得p型铜铁矿结构的半导体材料可以在较宽的范围内实现光学、电学和磁学性质的调控。此时，空穴传输层310的带隙可以通过组分调控在1.3eV-3.5eV范围内调节。与此同时，可以调节空穴传输层310的带隙与钙钛矿吸收层320、底电池100的带隙不同，从而避免空穴传输层310对叠层电池可吸收波段太阳能的吸收。
以AgGaO 2为例，其带隙为3.1eV，价带顶能级为-5.20eV，导带底能级为-2.10eV。一方面，AgGaO 2的价带顶能级接近钙钛矿吸收层320的HOMO能级(-5.30eV左右)，有利于空穴电荷的收集；另一方面，其导带低能级远离钙钛矿吸收层320的LUMO能级(-3.90eV左右)，可以有效阻挡电子的扩散。
上述空穴传输层310可以掺杂有金属或非金属元素。金属可以为Mg，非金属可以为N。此时，可以通过掺杂的方式调节空穴传输层310的带隙宽度，使得空穴传输层310更容易与n型重掺杂层220、钙钛矿吸收层320的能级进行匹配。
示例性的，制作空穴传输层310的p型铜铁矿结构的半导体材料中可以掺杂Mg、Ga、Sr中的一种或多种。此时，由于掺杂了金属元素，会导致空穴传输层310的价带顶能级发生较小的变化。例如，当制作空穴传输层310的材料CuCrO 2中掺杂Ga时，空穴传输层310的价带顶能级会降低0.05eV。
上述空穴传输层310可以采用真空沉积工艺形成在n型重掺杂层220上。所形成的空穴传输层310的厚度为5nm～100nm。示例性的，空穴传输层310的厚度可以为5nm、18nm、20nm、30nm、40nm、47nm、50nm、60nm、 70nm、77nm、85nm、90nm、95nm或100nm等。
当真空沉积p型铜铁矿结构的半导体材料形成空穴传输层310时，可以降低杂质对p型铜铁矿结构的半导体材料的污染，进而形成结晶度高、纯度高且致密性好、结合强度好的空穴传输层310，从而进一步提高空穴传输层310的空穴传输效率及其与n型重掺杂层220的结合性能，增大叠层电池的填充因子和光电转换效率。
上述钙钛矿吸收层320所包含的钙钛矿结构的半导体材料SDY 3中，S为CH 3NH 3阳离子、C 4H 9NH 3阳离子、NH 2＝CHNH 2阳离子、Cs阳离子中的一种或多种；D为Pb 2+、Sn 2+中的一种或两种的组合；Y为I -、Cl -、Br -中的一种或多种。钙钛矿吸收层320可以采用先共蒸形成阳离子锚定层，后旋涂阴离子盐并退火的方法制作。
上述透明导电层340形成在钙钛矿吸收层320的上方。当然，钙钛矿吸收层320和透明导电层340之间还可以包括电子传输层333，透明导电层340和底电池100上还形成有电极400。
本申请实施例还提供一种叠层电池的制作方法。以制作图3所示的n型硅异质结-钙钛矿叠层电池为例，其制作方法具体如下所述。
如图4所示，提供一n型晶体硅片。该n型晶体硅片可以选择电阻率为1Ω.cm-10Ω.cm，厚度为50μm-200μm的商业级M2硅片。n型晶体硅片依次经过抛光、制绒及清洗处理，形成具有绒面的n型单晶硅基底101。
如图5所示，在n型单晶硅基底101双侧沉积本征非晶硅钝化层，形成位于n型单晶硅基底101正面的第一钝化层102，位于n型单晶硅基底101背面的第二钝化层103。在实际应用中，可以采用等离子体化学气相沉积(PECVD)工艺、热丝化学气相沉积工艺或催化化学气相沉积工艺制作本征非晶硅钝化层。本征非晶硅钝化层的厚度可以为1nm-20nm。
如图6所示，在第一钝化层102上沉积n型掺杂层104，形成前场结构。n型掺杂层104的材料为非晶硅或微晶硅。在实际应用中，可以采用PECVD工艺、热丝化学气相沉积工艺或催化化学气相沉积工艺制作n型掺杂层104。n型掺杂层104的厚度可以为1nm-30nm。
如图7所示，在第二钝化层103上沉积p型掺杂层105，形成背面发射极。p型掺杂层的材料为非晶硅或微晶硅。在实际应用中，可以采用PECVD 工艺、热丝化学气相沉积工艺或催化化学气相沉积工艺制作p型掺杂层105。p型掺杂层105的厚度可以为1nm-30nm。
如图8所示，在p型掺杂层105上形成第一透明导电层106，实现光生载流子的收集和传输。在实际应用中，可以采用磁控溅射工艺制作该第一透明导电层106。具体的，第一透明导电层106的材料可以为氧化铟锡(ITO)、掺钨氧化铟(In 2O 3:W，缩写为IWO)、氧化铟锌(IZO)、掺钛氧化铟薄(ITiO)中的一种或多种。第一透明导电层106的厚度可以为30nm-120nm。所获得结构定义为底电池100，该底电池100具有绒面。
应理解，作为叠层电池的工艺起始步骤，可以是以提供一n型晶体硅片为工艺起点进行电池制作，也可以是以本申请定义的底电池100为工艺起点进行叠层电池制作。
如图9所示，在n型掺杂层104上形成形成钝化层210，以实现接触钝化。在实际应用中，可以采用磁控溅射工艺、化学气相沉积等工艺制作钝化层210。
如图10所示，在硅钝化层210上形成n型重掺杂层220。n型重掺杂层和下述的空穴传输层310靠近底电池的100的表面构成隧穿复合界面，实现光生载流子的隧穿复合收集。示例性的，n型重掺杂层220可以是磷掺杂的微晶硅薄膜。可以采用PECVD工艺、热丝化学气相沉积工艺或催化化学气相沉积工艺制作n型重掺杂层220。
如图11所示，在n型重掺杂层220上形成p型铜铁矿结构的半导体材料空穴传输层310。在背离底电池100的方向上，空穴传输层310的价带顶能级逐渐降低，且价带顶能级的变化范围为-4.5eV～-5.4eV。在实际应用中，可以采用真空沉积工艺制作空穴传输层310。具体的，真空沉积工艺可以为磁控溅射工艺、激光脉冲沉积工艺或热蒸发镀膜工艺。
举例说明，当采用磁控溅射工艺制作空穴传输层310时，形成厚度为5nm-100nm空穴传输层。
如图12所示，在空穴传输层310上形成钙钛矿吸收层320。具体包括：
采用共蒸法在空穴传输层310上形成碘化铅和溴化铯，总厚度250nm-1000nm。
在碘化铅和溴化铯上涂布甲脒氢碘酸盐(FAI)及甲脒氢溴酸盐(FABr) 混合溶液，FAI及FABr的混合溶液与碘化铅和溴化铯发生反应可以形成钙钛矿材料薄膜。FAI和FABr的摩尔浓度比可以为(2～4):1，FAI及FABr的混合溶液的溶剂可以为乙醇或异丙醇。
对钙钛矿材料薄膜进行退火处理，形成钙钛矿吸收层320。退火温度可以为100℃-200℃，退火时间可以为5min-30min，钙钛矿吸收层320的厚度可以为100nm-1000nm。钙钛矿吸收层320的材料组分为Cs xFA 1-xPb(Br yI 1-y) 3。
采用上述方法制作钙钛矿吸收层320时，由于阳离子盐迅速与底层碘化铅反应形成钙钛矿薄膜，过量未反应的阳离子盐溶液随旋涂过程被甩离加工界面，从而避免了堆积在金字塔型绒面谷底，因此，可以保形的在绒面上随形沉积均匀的钙钛矿薄膜。
如图13所示，在钙钛矿吸收层320上依次形成电子传输界面层331和漏电修复层332。在实际应用中，电子传输界面层331可以为LiF薄膜层，漏电修复层332可以为C60、富勒烯衍生物(PCBM)薄膜层。LiF薄膜层和C60薄膜层可以采用热蒸镀的方式制作，电子传输界面层331的厚度可以为0.1nm-10nm，漏电修复层332的厚度可以为1nm-20nm。在实际应用中电子传输界面层331和漏电修复层332，可以省略其中一个，也可以全部省略。
如图14所示，在电子传输界面层331上形成电子传输层333。在实际应用中，电子传输层333的材料可以为SnO 2，层厚可以为1nm-30nm，制作工艺可以为原子层沉积工艺(ALD)、化学气相沉积工艺、物理气相沉积工艺、溶液涂布工艺中的任一种。
如图15所示，在电子传输层333上形成第二透明导电层341，用以收集光生载流子。第二透明导电层341的材料、厚度及形成工艺可以参考第一透明导电层106。
如图16所示，在第一透明导电层106和第二透明导电层341上形成电极400，以汇集电流。在实际应用中，可以采用丝网印刷或掩膜蒸镀的方式制作电极400栅线。电极400的厚度可以为100nm-500nm，电极400的材料可以为银、铜、铝等导电性能较好的金属。图17a示出n型硅异质结-钙钛矿叠层电池正面示意图，图17b示出n型硅异质结-钙钛矿叠层背面正面示意图。如图17a和图17b所示，电极400形成于第一透明导电层106和第二透明导电层341上。
为了验证本申请实施例提供的叠层电池的制作方法制作的叠层电池的性能，下面以实施例和对比例相互比较的方式进行说明。
实施例一
本申请实施例提供的n型硅异质结-钙钛矿叠层电池的制作方法，具体如下所述：
第一步，提供一电阻率为4Ω.cm，厚度为180μm的n型M2硅片。对该硅片进行抛光、制绒及清洗处理，形成具有绒面的n型单晶硅基底。
第二步，利用PECVD设备在n型单晶硅基底双侧沉积本征非晶硅钝化层(厚度5nm)，形成位于n型单晶硅基底正面的第一钝化层，位于n型单晶硅基底背面的第二钝化层。
第三步，利用PECVD设备在第一钝化层上沉积磷掺杂(掺杂浓度10 20cm - 3)的N型非晶硅层(厚度10nm)，形成前场结构。
第四步，利用PECVD设备第二钝化层上沉积硼掺杂(掺杂浓度10 19cm - 3)的P型非晶硅层(厚度10nm)，形成背场发射极。
第五步，采用磁控溅射工艺在P型非晶硅层上制备ITO材质的第一透明导电层(厚度100nm)。
第六步，采用磁控溅射工艺在n型非晶硅层上形成钝化层。
第七步，利用PECVD设备在钝化层上形成磷掺杂的n型重掺杂层。
第八步，采用磁控溅射工艺在n型重掺杂层上制作AgGa xO 2材质的空穴传输层。通过使用三种组成不同的AgGa xO 2靶材制备三层复合型空穴传输材料，具体的，第一层采用组成为AgGa 0.9O 2的靶材，第二层采用组成为AgGaO 2的靶材，第三层采用组成为AgGa 1.1O 2的靶材。每一层空穴传输层厚度为5nm,空穴传输层总厚度为15nm。
第九步，采用共蒸法在空穴传输层上形成碘化铅和溴化铯，总厚度350nm。
配置FAI及FABr混合溶液，FAI和FABr的摩尔浓度比为3:1，溶剂为乙醇。取100μL的FAI及FABr混合溶液旋涂在碘化铅及溴化铯层上并发生反应，形成钙钛矿材料薄膜。
在150℃的温度下，对钙钛矿材料薄膜退火30min，形成致密均匀的钙钛矿吸收层(厚度500nm)，该吸收层材料组分为Cs xFA 1-xPb(BryI 1-y) 3。
第十步，采用热蒸镀工艺在钙钛矿吸收层上形成LiF薄膜层(厚度1nm) 和C60薄膜层(厚度10nm)。
第十一步，采用原子层沉积(ALD)工艺制作SnO 2材质的电子传输层(厚度10nm)。
第十二步，采用磁控溅射工艺在电子传输层上形成ITO材质的第二透明导电层(厚度100nm)。
第十三步，采用丝网印刷工艺在第一透明导电层和第二透明导电层上形成银电极栅线。
实施例二
本申请实施例提供的n型硅异质结-钙钛矿叠层电池的制作方法，具体如下所述：
第一步，提供一电阻率为1Ω.cm，厚度为50μm的n型硅片。对该硅片进行抛光、制绒及清洗处理，形成具有绒面的n型单晶硅基底。
第二步，利用PECVD设备在n型单晶硅基底双侧沉积本征非晶硅钝化层(厚度1nm)，形成位于n型单晶硅基底正面的第一钝化层，位于n型单晶硅基底背面的第二钝化层。
第三步，利用PECVD设备在第一钝化层上沉积磷掺杂(掺杂浓度10 20cm - 3)的N型非晶硅层(厚度1nm)，形成前场结构。
第四步，利用PECVD设备第二钝化层上沉积硼掺杂(掺杂浓度10 19cm - 3)的P型非晶硅层(厚度1nm)，形成背场发射极。
第五步，采用磁控溅射工艺在P型非晶硅层上制备ITO材质的第一透明导电层(厚度30nm)。
第六步，采用磁控溅射工艺在n型非晶硅层上形成钝化层。
第七步，利用PECVD设备在钝化层上形成磷掺杂的n型重掺杂层。
第八步，采用激光脉冲沉积工艺在n型重掺杂层上制作AgCr xO 2材质的空穴传输层。通过使用三种组成不同的AgCr xO 2靶材制备三层复合型空穴传输材料，具体的，第一层采用组成为AgCr 0.95O 2的靶材，第二层采用组成为AgCrO 2的靶材，第三层采用组成为AgCr 1.05O 2的靶材。每一层空穴传输层厚度为5nm,空穴传输层总厚度为15nm。在背离底电池的方向上，空穴传输层的价带顶能级逐渐降低，且价带顶能级的变化范围为-4.5eV～-5.4eV。
第九步，采用共蒸法在空穴传输层上形成碘化铅和溴化铯，总厚度250nm。
配置FAI及FABr混合溶液，FAI和FABr的摩尔浓度比为2:1，溶剂为乙醇。取100μL的FAI及FABr混合溶液旋涂在碘化铅及溴化铯层上并发生反应，形成钙钛矿材料薄膜。
在100℃的温度下，对钙钛矿材料薄膜退火5min，形成致密均匀的钙钛矿吸收层(厚度100nm)，该吸收层材料组分为Cs xFA 1-xPb(BryI 1-y) 3。
第十步，采用热蒸镀工艺在钙钛矿吸收层上形成LiF薄膜层(厚度0.1nm)和C60薄膜层(厚度1nm)。
第十一步，采用原子层沉积(ALD)工艺制作SnO 2材质的电子传输层(厚度1nm)。
第十二步，采用磁控溅射工艺在电子传输层上形成ITO材质的第二透明导电层(厚度30nm)。
第十三步，采用丝网印刷工艺在第一透明导电层和第二透明导电层上形成银电极栅线。
实施例三
本申请实施例提供的n型硅异质结-钙钛矿叠层电池的制作方法，具体如下所述：
第一步，提供一电阻率为10Ω.cm，厚度为200μm的n型硅片。对该硅片进行抛光、制绒及清洗处理，形成具有绒面的n型单晶硅基底。
第二步，利用PECVD设备在n型单晶硅基底双侧沉积本征非晶硅钝化层(厚度20nm)，形成位于n型单晶硅基底正面的第一钝化层，位于n型单晶硅基底背面的第二钝化层。
第三步，利用PECVD设备在第一钝化层上沉积磷掺杂(掺杂浓度10 20cm - 3)的N型非晶硅层(厚度30nm)，形成前场结构。
第四步，利用PECVD设备第二钝化层上沉积硼掺杂(掺杂浓度10 19cm - 3)的P型非晶硅层(厚度30nm)，形成背场发射极。
第五步，采用磁控溅射工艺在P型非晶硅层上制备ITO材质的第一透明导电层(厚度120nm)。
第六步，采用磁控溅射工艺在n型非晶硅层上形成钝化层。
第七步，利用PECVD设备在钝化层上形成磷掺杂的n型重掺杂层。
第八步，采用激光脉冲沉积工艺在n型重掺杂层上制作AgGa xO 2材质的 空穴传输层。通过使用三种组成不同的AgGa xO 2靶材制备三层复合型空穴传输材料，具体的，第一层采用组成为AgGa 0.95O 2的靶材，第二层采用组成为AgGaO 2的靶材，第三层采用组成为AgGa 1.05O 2的靶材。每一层空穴传输层厚度为25nm,空穴传输层总厚度为75nm。在背离底电池的方向上，空穴传输层的价带顶能级逐渐降低，且价带顶能级的变化范围为-4.5eV～-5.4eV。
第九步，采用共蒸法在空穴传输层上形成碘化铅和溴化铯，总厚度1000nm。
配置FAI及FABr混合溶液，FAI和FABr的摩尔浓度比为4:1，溶剂为乙醇。取100μL的FAI及FABr混合溶液旋涂在碘化铅及溴化铯层上并发生反应，形成钙钛矿材料薄膜。
在200℃的温度下，对钙钛矿材料薄膜退火30min，形成致密均匀的钙钛矿吸收层(厚度1000nm)，该吸收层材料组分为Cs xFA 1-xPb(BryI 1-y) 3。
第十步，采用热蒸镀工艺在钙钛矿吸收层上形成LiF薄膜层(厚度10nm)和C60薄膜层(厚度20nm)。
第十一步，采用原子层沉积(ALD)工艺制作SnO 2材质的电子传输层(厚度30nm)。
第十二步，采用磁控溅射工艺在电子传输层上形成ITO材质的第二透明导电层(厚度120nm)。
第十三步，采用丝网印刷工艺在第一透明导电层和第二透明导电层上形成银电极栅线。
对比例一
本对比例提供的叠层电池的制作方法与上述实施例一记载的方法基本相同，区别仅在于：空穴传输层的材质为Spiro-TTB，空穴传输层的制备工艺为热蒸发工艺。空穴传输层中各处的价带顶能级相同，且钝化层与空穴传输层之间具有p型重掺杂层。
对比例二
本对比例提供的叠层电池的制作方法与上述实施例一记载的方法基本相同，区别仅在于：空穴传输层的材质为氧化镍。空穴传输层中各处的价带顶能级相同，且钝化层与空穴传输层之间具有p型重掺杂层。
为验证叠层电池的性能，对实施例一、对比例一和对比例二所制备的器件进行扫描电子显微镜(SEM)和I-V测试，并对比各器件的光电转换效率、填 充因子、开路电压、短路电流等性能参数(表1)。
图18示出实施例一所制备的叠层电池的表面形貌SEM图。图19示出实施例一所制备的叠层电池截面的SEM图像。从图18可以看出，实施例一所制备的叠层电池的表面为金字塔绒面。从图19可以看出钙钛矿吸收层的下表面与空穴传输层紧密贴合，未有观察到金字塔尖的缺陷或塔间谷底的累积。并且钙钛矿吸收层未有观察到界面空洞和剥离现象，钙钛矿薄膜生长均匀，未观察到明显的晶界缺陷，可见钙钛矿吸收层结晶度较高。可见，实施例一所制备的叠层电池的顶电池各功能层能够沿着底电池金字塔绒面起伏随形分布，且空穴传输层与钙钛矿吸收层界面接触较好，钙钛矿吸收层成膜质量较好。
图20示出实施例一、对比例一及对比例二所制备的叠层电池在AM1.5G太阳光强射下的I-V曲线。由图20可知，实施例一制备的叠层电池的短路电流J sc为20.2mA/cm 2，开路电压V oc为1.69V，填充因为FF为77％，最终电池转换效率为26.3％。图21示出对比例一和对比例二提供的叠层电池能带示意图；图22示出实施例一至三的叠层电池的能带示意图。对比图21和图22可知，本申请实施例采用价带顶能级逐渐降低的空穴传输层代替p型重掺杂层(省略p型重掺杂)后，空穴传输层的价带顶能级比较接近钙钛矿吸收层的价带能级，空穴传输层的导带低能级接近n型重掺杂层的导带能级，使得接触势垒较小，可以提高空穴传输效率，且载流子复合效率较高。
实施例一所制备的叠层电池的各项器件性能参数，明显优于传统叠层电池。表1示出各实施例和对比例所制备的叠层电池的性能参数。
表1不同叠层电池的性能参数对比表
Figure PCTCN2021122897-appb-000002
Figure PCTCN2021122897-appb-000003
由图20及表1可知，实施例一制备的叠层电池的短路电流J sc为20.2mA/cm 2，开路电压V oc为1.69V，填充因为FF为77％，最终电池转换效率为26.3％。实施例一所制备的叠层电池的各项器件性能参数，明显优于对比例一和对比例2的传统叠层电池。对比实施例一和实施例二可知，调整空穴传输层的材料，可以对叠层电池的填充因子进行精细调控。对比实施例一和实施例三可知，采用不同的真空沉积工艺，均可以获得较好的叠层电池的性能。
尽管在此结合各实施例对本申请进行了描述，然而，在实施所要求保护的本申请过程中，本领域技术人员通过查看附图、公开内容、以及所附权利要求书，可理解并实现公开实施例的其他变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包括这些改动和变型在内。

Claims (20)

  1. 一种叠层电池，其特征在于，包括：
    底电池；
    形成在所述底电池上的空穴传输层，所述空穴传输层的材料包括p型铜铁矿结构的半导体材料，在背离所述底电池的方向上，所述空穴传输层的价带顶能级逐渐降低；
    形成在所述空穴传输层上的钙钛矿吸收层；
    以及形成在所述钙钛矿吸收层上方的透明导电层。
  2. 根据权利要求1所述的叠层电池，其特征在于，所述p型铜铁矿结构的半导体材料的化学通式为ABC x，其中，A包括Cu +、Ag +、Pd +、Sr +、Pt +中的一种或多种，B包括B 3+、Al 3+、Ga 3+、In 3+、Cr 3+、Fe 3+、Sc 3+及三价稀土阳离子中的一种或多种，C为氧族元素，包括O、S、Se、Te中的一种或多种，x在1.95～2.6之间。
  3. 根据权利要求1所述的叠层电池，其特征在于，所述空穴传输层在厚度方向上具有多个子层，所述各子层B元素含量从背离所述钙钛矿吸收层到靠近所述钙钛矿的吸收层的方向上依次增加。
  4. 根据权利要求1所述的叠层电池，其特征在于，所述空穴传输层的厚度为5nm～100nm；和/或，
    所述空穴传输层的价带顶能级的变化范围为-4.5eV～-5.4eV。
  5. 根据权利要求1-4任一项所述的叠层电池，其特征在于，所述底电池的顶层为n型重掺杂层，所述n型重掺杂层与所述空穴传输层接触而形成载流子复合界面。
  6. 根据权利要求5所述的叠层电池，其特征在于，所述叠层电池还包括位于所述底电池和所述n型重掺杂层之间的钝化层。
  7. 根据权利要求1～4任一项所述的叠层电池，其特征在于，所述底电池为晶体硅底电池、多晶硅底电池、铸锭单晶硅底电池、铜铟镓硒底电池、钙钛矿底电池、砷化镓底电池、有机光伏底电池中的任一种。
  8. 一种权利要求1～7任一项所述的叠层电池的制作方法，其特征在于，包括：
    提供一底电池；
    采用真空沉积工艺在所述底电池上形成空穴传输层，所述空穴传输层 的材料包括p型铜铁矿结构的半导体材料，在背离所述底电池的方向上，所述空穴传输层的价带顶能级逐渐降低；
    在所述空穴传输层上形成钙钛矿吸收层；
    在所述钙钛矿吸收层上形成电子传输层和透明导电层。
  9. 根据权利要求8所述的叠层电池的制作方法，其特征在于，所述真空沉积工艺为磁控溅射工艺、激光脉冲沉积工艺或热蒸发镀膜工艺。
  10. 根据权利要求8或9所述的叠层电池的制作方法，其特征在于，在所述空穴传输层上形成钙钛矿吸收层包括：
    采用共蒸法在所述空穴传输层上形成碘化铅和溴化铯，
    在碘化铅和溴化铯上涂布甲脒氢碘酸盐及甲脒氢溴酸盐混合溶液，形成钙钛矿材料薄膜；
    对钙钛矿材料薄膜进行退火处理，形成钙钛矿吸收层。
  11. 一种叠层电池，其特征在于，包括：
    底电池；
    形成在所述底电池上的空穴传输层，所述空穴传输层的材料包括p型铜铁矿结构的半导体材料，在背离所述底电池的方向上，所述空穴传输层的价带顶能级逐渐降低；
    形成在所述空穴传输层上的钙钛矿吸收层；
    以及形成在所述钙钛矿吸收层上方的透明导电层。
  12. 根据权利要求11所述的叠层电池，其特征在于，所述p型铜铁矿结构的半导体材料的化学通式为AB αC x，其中，A包括Cu +、Ag +、Pd +、Sr +、Pt +中的一种或多种，B包括B 3+、Al 3+、Ga 3+、In 3+、Cr 3+、Fe 3+、Sc 3+及三价稀土阳离子中的一种或多种，C为氧族元素，包括O、S、Se、Te中的一种或多种，x在1.95～2.6之间，α在0.9-1.1之间。
  13. 根据权利要求12所述的叠层电池，其特征在于，所述空穴传输层中B元素的含量从背离所述钙钛矿吸收层到靠近所述钙钛矿的吸收层的方向上依次增加。
  14. 根据权利要求11所述的叠层电池，其特征在于，所述空穴传输层的厚度为5nm～100nm；和/或，所述空穴传输层的价带顶能级的变化范围为-4.5eV～-5.4eV。
  15. 根据权利要求11-14任一项所述的叠层电池，其特征在于，所述底电池的顶层为n型重掺杂层，所述n型重掺杂层与所述空穴传输层接触而 形成载流子复合界面。
  16. 根据权利要求15所述的叠层电池，其特征在于，所述叠层电池还包括位于所述底电池和所述n型重掺杂层之间的钝化层。
  17. 根据权利要求11～14任一项所述的叠层电池，其特征在于，所述底电池为晶体硅底电池、多晶硅底电池、铸锭单晶硅底电池、铜铟镓硒底电池、钙钛矿底电池、砷化镓底电池、有机光伏底电池中的任一种。
  18. 一种权利要求11～17任一项所述的叠层电池的制作方法，其特征在于，包括：
    提供一底电池；
    采用真空沉积工艺在所述底电池上形成空穴传输层，所述空穴传输层的材料包括p型铜铁矿结构的半导体材料，在背离所述底电池的方向上，所述空穴传输层的价带顶能级逐渐降低；
    在所述空穴传输层上形成钙钛矿吸收层；
    在所述钙钛矿吸收层上形成电子传输层和透明导电层。
  19. 根据权利要求18所述的叠层电池的制作方法，其特征在于，所述真空沉积工艺为磁控溅射工艺、激光脉冲沉积工艺或热蒸发镀膜工艺。
  20. 根据权利要求18或19所述的叠层电池的制作方法，其特征在于，在所述空穴传输层上形成钙钛矿吸收层包括：
    采用共蒸法在所述空穴传输层上形成碘化铅和溴化铯，
    在碘化铅和溴化铯上涂布甲脒氢碘酸盐及甲脒氢溴酸盐混合溶液，形成钙钛矿材料薄膜；
    对钙钛矿材料薄膜进行退火处理，形成钙钛矿吸收层。
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