WO2010024240A1 - Bipolar silicon carbide semiconductor device and method for manufacturing same - Google Patents

Bipolar silicon carbide semiconductor device and method for manufacturing same Download PDF

Info

Publication number
WO2010024240A1
WO2010024240A1 PCT/JP2009/064770 JP2009064770W WO2010024240A1 WO 2010024240 A1 WO2010024240 A1 WO 2010024240A1 JP 2009064770 W JP2009064770 W JP 2009064770W WO 2010024240 A1 WO2010024240 A1 WO 2010024240A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
base
resistance layer
emitter
silicon carbide
Prior art date
Application number
PCT/JP2009/064770
Other languages
French (fr)
Japanese (ja)
Inventor
賢一 野中
Original Assignee
本田技研工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 本田技研工業株式会社 filed Critical 本田技研工業株式会社
Priority to JP2010526712A priority Critical patent/JP5469068B2/en
Publication of WO2010024240A1 publication Critical patent/WO2010024240A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Definitions

  • the present invention relates to a bipolar silicon carbide semiconductor device and a method for manufacturing the same, and in particular, is a bipolar silicon carbide semiconductor device having a normal four-layer structure, in which a main current flowing between main electrodes and a control current flowing through a control electrode are
  • the present invention relates to a bipolar silicon carbide semiconductor device suitable for suppressing recombination between the two and increasing the current amplification factor, and a method for manufacturing the same.
  • SiC Silicon carbide
  • junction SiC power devices include static induction transistors (Static Induction Transistor, “SIT”), junction field effect transistors (Junction Field Effect Transistor, “JFET”), or bipolar transistors (Bipolar Junction Transistor, “BJT”). and so on.
  • SIT Static Induction Transistor
  • JFET Junction Field Effect Transistor
  • BJT Bipolar Junction Transistor
  • BJT is stacked on the low resistance n + -type 4H-SiC (0001) plane 8 degree off substrate in the order of n ⁇ -type high resistance region, p-type base region, and n + -type emitter region from the bottom. It is formed.
  • the emitter region is composed of a number of elongated regions. Electrodes for establishing electrical connection to the outside are formed in the emitter region, base region, and collector region.
  • FIG. 13 shows a cross section of the BJT disclosed in Non-Patent Document 1.
  • the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region.
  • the base contact region 505 of the p-type low resistance region is formed.
  • a collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503 (base contact region 505), and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.
  • Patent Document 1 As an example of a conventional BJT with improved device characteristics (current amplification factor), there is one having a structure described in Patent Document 1.
  • the BJT disclosed in Patent Document 1 has a first n-type high resistance layer, a p-type base region, and a second n-type layer on the n + -type 4H—SiC (0001) surface substrate serving as a collector region from below.
  • a type high resistance layer and an n + type emitter region are stacked in this order.
  • the emitter region is separated and formed by etching in a predetermined planar pattern shape from the upper surface to the middle of the n + -type emitter region and the second n-type high resistance layer in the stacked structure. .
  • the BJT has a plurality of emitter regions separated on the upper surface based on a predetermined pattern shape. In the region between the separated emitter regions, an Al ion implantation process is subsequently performed to form a p-type base contact region in contact with the base region. Each of the plurality of separated emitter regions is surrounded by a base contact region when viewed in a BJT planar shape.
  • the BJT disclosed in Patent Document 1 has a structure in which the SiC surface of the BJT is covered with a surface recombination suppressing semiconductor layer between the emitter region and the base contact region.
  • the surface recombination suppressing semiconductor layer has a function of suppressing recombination between electrons flowing out from the emitter region and holes flowing out from the base contact region. This suppresses recombination of electrons from the emitter region and holes from the base contact region, and achieves an improvement in the current amplification factor of the junction type semiconductor layer device.
  • a control electrode portion called a base is formed by a pn junction.
  • Ic main current
  • control current Ib control current
  • recombination of holes flowing from the control electrode (carrier of the control current Ib) and electrons flowing between the main electrodes (carrier of the main current Ic) can be mentioned.
  • the value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.
  • the SiC surface is known as a site where recombination is likely to occur.
  • various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1.
  • a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface.
  • a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered.
  • the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration.
  • a surface recombination suppressing semiconductor layer By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.
  • the emitter region is etched until the surface of the base region is exposed. At this time, the base region layer needs to be slightly shaved. For this reason, since the base region becomes thin, the resistance increases, and the base resistance varies due to variations in the etching substrate surface. In order to improve the current amplification factor of the BJT, it is desirable to reduce the thickness of the base region. However, if the thickness of the base region is reduced, the increase or variation in the base resistance due to the above-described etching process of the emitter region becomes remarkable. Become. For a conventional BJT having a four-layer structure, a device that achieves both a high current gain and a small and stable base resistance has not been realized.
  • an object of the present invention is a conventional BJT having a four-layer structure, which reduces the recombination probability of electrons and holes, and controls the main current flowing between the main electrodes and the control electrode.
  • An object of the present invention is to provide a bipolar silicon carbide semiconductor device capable of suppressing recombination between currents, improving a current amplification factor, and realizing a small and stable base resistance, and a method for manufacturing the same.
  • a first bipolar silicon carbide semiconductor device (corresponding to claim 1) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer.
  • a base region formed thereon, an emitter region formed of a low-resistance layer and bonded to the base region; a low-resistance base contact region formed around the emitter region and bonded to the base region; and a base contact region Near the surface between the emitter region, a recombination suppression region having the same conductivity type as the base region and higher than its resistivity, or a recombination suppression region having the same conductivity type as the emitter region and higher than its resistivity It is characterized by having.
  • a second bipolar silicon carbide semiconductor device (corresponding to claim 2) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer.
  • the base region formed above, an emitter region composed of a low resistance layer, joined to the base region, a low resistance base contact region formed around the emitter region and joined to the base region, and the base region, It is characterized by having a buried region that is in contact with the base contact region and has the same conductivity type as the base region and has a resistivity equal to or lower than the resistivity.
  • a third bipolar silicon carbide semiconductor device (corresponding to claim 3) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer.
  • a base region formed on the base region, an emitter region joined to the base region, a low resistance base contact region formed around the emitter region and joined to the base region, and a high resistance layer A buried region that is in contact with the base region and has the same conductivity type as that of the base region and has a resistivity higher than that of the base region, or a recombination suppression region that has the same conductivity type as that of the high resistance region and has a resistivity higher than that of the base region. It is characterized by having.
  • the collector region is a low-resistance layer of the first conductivity type and the emitter region is a low-resistance layer of the first conductivity type in the above configuration.
  • the high resistance layer is of the first conductivity type, and the base region is of the second conductivity type.
  • a first bipolar silicon carbide semiconductor device manufacturing method includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer
  • a recombination suppression region having the same conductivity type as the base region and higher in resistivity than the base region exposed by etching, or having the same conductivity type as the emitter region and its resistance
  • a second bipolar silicon carbide semiconductor device manufacturing method includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer And a fifth step of forming a buried region in the base region in contact with the base contact region and having the same conductivity type as the base region and having a resistivity equal to or lower than the resistivity. And a sixth step of forming a base contact region bonded to the base region.
  • a third bipolar silicon carbide semiconductor device manufacturing method includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer And a fourth step of contacting the base region with the high-resistance layer and having the same conductivity type as that of the base region and higher than its resistivity, or having the same conductivity type as that of the emitter region and the resistivity thereof. A fifth step of forming a higher buried region and a sixth step of forming a base contact region bonded to the base region.
  • a collector electrode, an emitter electrode, and a base electrode are formed in each of the collector region, the emitter region, and the base contact region. And a step of forming an upper layer electrode above the emitter electrode and the base electrode.
  • the bipolar silicon carbide semiconductor device has the following effects. First, since the recombination suppression region is formed on the base surface from the base region to the emitter region, it prevents the electron or hole from approaching the recombination level formed on the surface of the silicon carbide semiconductor, thereby increasing the current amplification factor. Can be increased.
  • the base region or the buried region having a higher resistance than the high resistance layer is formed in the high resistance layer, electrons from the high resistance layer can be prevented from approaching the base region, and the current amplification factor can be increased. .
  • the base resistance value can be reduced and variations can be suppressed, and the device characteristics of BJT can be made uniform. can do.
  • the bipolar silicon carbide semiconductor device is provided with the layered recombination suppressing semiconductor region at a required location as described above, and therefore, electrons flowing from the emitter and Recombination of holes flowing from the base can be suppressed, and a bipolar silicon carbide semiconductor device having a high current gain can be easily and reliably manufactured.
  • FIG. 3 is a partial longitudinal sectional view of a bipolar semiconductor device (BJT) according to a first embodiment of the present invention, and is an enlarged sectional view taken along line AA of FIG. 1 is a plan view of a part of a bipolar semiconductor device according to a first embodiment. It is a fragmentary longitudinal cross-section explaining the problem of operation
  • movement of the bipolar type semiconductor device by 1st Example. 3 is a flowchart illustrating a method for manufacturing a bipolar semiconductor device according to the first embodiment.
  • FIG. 5 is a partial longitudinal sectional view of a bipolar semiconductor device according to a second embodiment of the present invention. It is a fragmentary longitudinal cross-sectional view explaining operation
  • FIG. 6 is a longitudinal sectional view of a bipolar semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 6 is a longitudinal sectional view of a bipolar semiconductor device according to a fifth embodiment of the present invention. It is the longitudinal cross-sectional view which showed the structure of the conventional bipolar type semiconductor device.
  • FIGS. 1 to 6B A first embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS. 1 to 6B.
  • This bipolar semiconductor device shows an example of a conventional BJT having a general four-layer structure.
  • the BJT 10 includes, for example, five emitter electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device. These emitter electrodes 19 are surrounded by a base electrode 20.
  • the BJT 10 has a collector region 11 formed of an n-type low resistance layer (n + layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal.
  • An emitter region 12 made of an n-type low resistance layer (n + layer) formed on the upper side surface portion is provided.
  • a layer forming the collector region 11 is a substrate.
  • a base electrode 20 is formed around each of the plurality of emitter electrodes 19 so as to surround the emitter electrode 19. This means that the periphery of the emitter region 12 located below the emitter electrode 19 is surrounded by the p-type base contact region 13 located below the base electrode 20.
  • the base contact region 13 is formed up to a predetermined depth position.
  • BJT 10 between the upper emitter region 12 and a lower collector region 11, n-type high-resistance layer from the lower side (n - layer) and 14 and p-type base region 15 is formed by stacking Yes.
  • the base region 15 is formed so as to be in contact with and electrically connected to the base contact region 13. In other words, the base contact region 13 is formed so as to be embedded at a predetermined position on the base region 15.
  • n-type is “first conductivity type” and the “p-type” is “second conductivity type”.
  • the p + type base region 15 is further interposed between the p + type base contact region 13 formed on a part of the surface of the layered p type base region 15 and the emitter region 12.
  • a layered recombination suppression region 16 is provided on the exposed surface portion so as to cover the surface portion.
  • the depth of the recombination suppression region 16 is substantially equal to the depth of the base contact region 13.
  • the recombination suppression region 16 is a high-resistance semiconductor and is “p ⁇ ” or “n ⁇ ”.
  • the base contact region 13 is formed so as to come into contact with the surface of the base region 15 and further enter the inside of the base region 15 from the surface.
  • the collector electrode 18 is bonded to the lower surface of the collector region 11
  • the emitter electrode 19 is bonded to the upper surface of the emitter region 12
  • the base contact region 13 A base electrode 20 is joined to the upper surface.
  • the exposed surface between the emitter electrode 19 and the base electrode 20 is covered with a surface protective film 17 and is protected thereby.
  • an upper layer electrode 21 is provided above each of the emitter electrode 19 and the base electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.
  • the main current is an electron flow that flows from the emitter region 12 (or the emitter electrode 19) to the collector region 11 (or the collector electrode 18).
  • the emitter region 12 and the collector region 11 are main electrode regions for flowing a main current.
  • Energization (ON) and non-energization (OFF) of the main current are based on a base voltage applied to the base electrode 20, that is, a control signal applied between the base contact region 13 and the base region 15 and the emitter region 12. Be controlled.
  • the applied voltage between the base and the emitter is 0 V or less, the BJT 10 does not flow main current and is turned off.
  • the BJT 10 When a voltage of a certain level or higher is applied between the base and the emitter, the BJT 10 is turned on due to the main current flowing. In the ON state, the pn junction formed between the base region 15 and the emitter region 12 is forward-biased, and a hole current that is a control current flows from the base region 15 to the emitter region 12.
  • FIG. 3 shows a BJT 10A having a conventional structure.
  • the same elements as those described in FIG. In the structure of the BJT 10A, in the base region 15, a large number of recombination levels 22 are formed in the vicinity of the SiC surface between the base contact region 13 and the emitter region 12. Therefore, some of the electrons 23 of the main current I1 flowing from the emitter region 12 toward the collector region 11 and the holes 24 flowing from the base contact region 13 are recombined at the recombination level 22. Such recombination of electrons 23 and holes 24 occurs frequently at the interface between the base region 15 and the high resistance layer 14. As a result, an invalid base current that does not contribute to the operation of the BJT 10A flows, and the current amplification factor of the BJT 10A is reduced.
  • a layer-like layer is formed on the surface of the base region 15 exposed between the base contact region 13 and the emitter region 12 and its vicinity.
  • a coupling suppression region 16 is formed.
  • the recombination suppressing region 16 is formed of a “p ⁇ ” or “n ⁇ ” semiconductor region, and forms a high potential barrier against the electrons 23 or the holes 24 and also has a high resistance layer having a low hole or electron concentration. It has become. Due to the existence of the recombination suppression region 16, holes 24 flowing from the base contact region 13 to the base region 15 do not easily flow into the recombination suppression region 16 in FIG.
  • Electrons flowing from the region 12 are also difficult to flow near the SiC surface. As a result, as shown in FIG. 4, the electrons 23 flowing out from the emitter region 12 flow toward the collector region 11 as the main current I2 without recombining with the holes, thereby improving the current amplification factor of the BJT 10. Can do.
  • the implantation concentration is extremely low and the energy required for ion implantation is low compared to the ion implantation for forming the base contact region 13. Therefore, in the ion implantation for forming the recombination suppression region 16, the density of recombination levels can be suppressed low.
  • the BJT 10 is designed with a target of a blocking voltage of 600V, for example.
  • a low resistance n-type 4H—SiC substrate turned off by 8 degrees from the (0001) plane is used as the substrate portion.
  • the substrate portion becomes the collector region 11.
  • the n-type high resistance layer 14 on the substrate is a layer for blocking a high voltage applied between the emitter and the collector.
  • the high resistance layer 14 is set to have a thickness of 10 ⁇ m and an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 , for example, so as to block a voltage of 600 V or higher.
  • the p-type base region 15 on the high resistance layer 14 has a thickness and an impurity concentration so as not to be depleted when a high voltage is applied between the emitter and the collector.
  • the p-type base region 15 has a thickness of 0.2 to 0.5 ⁇ m and an impurity concentration of about 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3 .
  • a low resistance n-type emitter region 12 having a thickness of 0.5 to 2.0 ⁇ m and an impurity concentration of 1 to 5 ⁇ 10 19 cm ⁇ 3 is provided.
  • a low-resistance base contact region 13 is formed around the emitter region 12.
  • the planar shape of the emitter region 12 is an elongated island shape.
  • One BJT 10 includes a plurality of emitter regions 12.
  • the dimensions of one emitter region 12 are about 3 to 10 ⁇ m in width and about 100 to 1000 ⁇ m in length.
  • the period of the unit structure including the base contact region 13 and the emitter region 12 is about 10 to 30 ⁇ m.
  • FIG. 5 is a flowchart showing each process of the manufacturing method.
  • 6A and 6B are longitudinal sectional views showing structures manufactured by each process.
  • the manufacturing method of the BJT 10 includes the following processes (1) to (10) (steps S11 to S20). As shown in FIG. 5, each process is executed in the order from step S11 to step S20.
  • step S11 High resistance layer forming process
  • step S12 Base region formation process
  • step S13 Low resistance layer formation process
  • step S14 Emitter etching process
  • step S15 Recombination suppression region formation process
  • step S17 Base contact region formation process
  • step S18 Surface protective film formation process
  • step S19 Electrode formation process
  • step S20 Upper layer electrode formation process
  • the structure shown in (a) of FIG. 6A is formed by performing the above steps S11 to S13.
  • step S11 nitrogen having a thickness of 10 ⁇ m and a concentration of 1 ⁇ 10 16 cm ⁇ 3 is doped as an impurity on the n-type substrate 40 formed of SiC by an epitaxial growth method.
  • a high resistance layer 41 is grown. “4H—SiC (0001) 8 ° off” is used for the substrate 40.
  • the substrate 40 becomes the collector region 11 of the n-type low resistance layer described above.
  • step S12 an epitaxial growth method is performed on the n-type high resistance layer 41 with aluminum (Al) as an impurity at a concentration of 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3 to 0.2 to A 0.5 ⁇ m p-type base region 42 is grown.
  • Al aluminum
  • step S13 nitrogen having a thickness of 0.5 to 2.0 ⁇ m and a concentration of 1 to 5 ⁇ 10 19 cm ⁇ 3 is formed as an impurity on the n-type base region 42 by an epitaxial growth method.
  • a doped n-type low resistance layer 43 is grown.
  • the low resistance layer 43 is a portion for forming the emitter region 12 described above.
  • step S14 in the structure shown in FIG. 6A (a), a silicon oxide film 51 is deposited on the upper surface by CVD, photolithography is performed, and then silicon oxide is formed by RIE. The film 51 is etched. Thus, a mask is formed. Then, using this silicon oxide film 51, SiC etching is performed on the low resistance layer 43 by RIE, and the emitter region 12 is formed using the low resistance layer 43. SF 6 gas or the like is used for RIE of SiC etching. The resulting structure is shown in FIG. 6A (b).
  • the recombination suppression region 16 is formed using the mask 51 shown in FIG. 6A (b) as it is. .
  • the recombination suppression region 16 is formed by performing ion implantation of nitrogen as an impurity (ion species). Ions are implanted into all regions etched by the emitter etching process (step S15).
  • the ion implantation amount is set to a value approximately equal to or around the impurity concentration of the base region 42.
  • the ion implantation amount is desirably about 3 to 5 ⁇ 10 17 cm ⁇ 3 .
  • the recombination suppression region 16 since the recombination suppression region 16 only needs to include a recombination level in the vicinity of the surface, its depth may be about 0.1 to 0.2 ⁇ m. Therefore, the implantation energy can be suppressed to as low as about 100 keV, and the generation of crystal defects in the ion implantation process can be suppressed.
  • step S16 In the base contact region forming process (step S16), first, as shown in FIG. 6A (d), a mask 52 is formed so that the surface portion for forming the base contact region 13 is exposed.
  • the mask 52 is formed by depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, ion implantation is performed to form the base contact region 13.
  • the implanted ions are aluminum (Al), and the depth of implantation is, for example, 0.2 ⁇ m.
  • the ion implantation amount is 1 ⁇ 10 18 to 10 20 cm ⁇ 3 , and the energy required for ion implantation is approximately 200 KeV.
  • the recombination suppression region 16 is formed on the surface of the base region 15 between the base contact region 13 and the emitter region 12 by the above steps S15 and S16.
  • the purpose of providing the recombination suppression region 16 is to keep electrons coming from the emitter region 12 away from the SiC surface of the recombination suppression region 16.
  • step S17 in the process of activating the ion implantation layer (step S17), after the ion implantation, the implanted ions are electrically activated in the semiconductor, and a heat treatment is performed to eliminate crystal defects generated by the ion implantation ( FIG. 6B (e)).
  • a heat treatment is performed to eliminate crystal defects generated by the ion implantation ( FIG. 6B (e)).
  • both the implanted ions in the base contact region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time.
  • heat treatment is performed at a high temperature of about 1700 to 1800 ° C. for about 10 minutes.
  • argon gas (Ar) is used as the atmospheric gas.
  • step S18 In the process of forming the surface protective film (step S18), as shown in FIG. 6B (f), first, in order to remove the surface layer generated in the ion implantation process and the activation process, the oxide film is removed after the thermal oxidation. Perform sacrificial oxidation.
  • the oxidation condition is, for example, 1100 ° C. for 20 hours in dry oxygen. Hydrofluoric acid is used to remove the oxide film.
  • thermal oxidation is performed again to form an oxide film 53.
  • the temperature is 1100 ° C.
  • the time is 5 hours
  • the atmosphere is wet.
  • POA Post Oxidation Anneal
  • heat treatment is performed to reduce the impurity level at the interface of the SiC oxide film.
  • POA is performed in a hydrogen, nitrogen oxide (NO, N 2 O) or argon atmosphere at a high temperature of about 800 to 1300 ° C. for about 10 to 30 minutes.
  • a CVD oxide film or a CVD nitride film is formed.
  • the emitter electrode 19, the base electrode 20, and the collector electrode 18 are formed on the surfaces of the emitter region 12 (low resistance layer 43), the base contact region 13, and the collector region 11 (substrate 40), respectively. It forms (FIG. 6B (g)).
  • the remaining oxide film 53 becomes the surface protective film 17 described above.
  • the emitter electrode 19 and the collector electrode 18 are made of nickel or titanium, and the base electrode 20 is made of titanium or aluminum.
  • Each electrode 18, 19, 20 is formed by vapor deposition or sputtering. For the formation of the electrode pattern, dry etching, wet etching, lift-off method or the like is used.
  • heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion.
  • the heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.
  • step S20 the upper layer electrode formation process (step S20) is executed.
  • an upper layer electrode 54 for taking out a plurality of separated emitter electrodes 19 as one electrode is formed (FIG. 6B (h)).
  • the silicon oxide film or the like in the emitter electrode 19 is removed by photolithography and etching.
  • the upper layer electrode 54 is deposited.
  • aluminum (Al) is used as the material of the upper electrode 54.
  • the BJT 10 shown in FIGS. 1 and 2 is manufactured.
  • the BJT 10 is a high-performance semiconductor device having normally-off characteristics.
  • the combinations of the first and second conductivity types such as the collector region, the emitter region, the high resistance layer, the base region, the base contact region, and the recombination suppression region can be reversed. . This also applies to the other embodiments described below.
  • FIG. 7 A second embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS.
  • the bipolar semiconductor device of the second embodiment is also BJT.
  • elements that are substantially the same as those described in FIG. 1 are given the same reference numerals.
  • the emitter region 12 is etched until the surface of the base region 15 is exposed.
  • the thickness of the base layer is reduced, and as a result, the resistance value of the base is increased.
  • the base resistance value varies between wafers or between wafers due to variations in etching depth within a wafer or between wafers.
  • a p-type semiconductor having a resistivity equal to or lower than that of the base region in a region corresponding to the region of the base surface exposed by etching in the base region 15 formed in a layer shape A low resistance buried region 61 made of p + or p ⁇ ) is provided.
  • the surface recombination suppression region 16 is not formed as in the first embodiment.
  • Other structures are the same as those of the first embodiment.
  • the hole current flowing from the base contact region 13 to the base region 15 flows near the surface in the conventional example shown in FIG. 3, whereas the resistance value as shown in FIG. It flows to the lower low resistance buried region 61. Therefore, recombination near the surface of base region 15 is reduced, and the current amplification factor is improved.
  • the resistance of the base region 15 is determined by the resistance value of the low-resistance buried region 61. As a result, it is possible to increase the resistance and variation of the base region 15 caused by the etching.
  • the impurity concentration of the p-type base region 15 are as 4 ⁇ 10 17 ⁇ 2 ⁇ 10 18 cm -3 as described above, the concentration of more than the same level as the base region 15 the impurity concentration of the low-resistance buried region 61
  • the impurity concentration of the p-type base region 15 is, for example, 4 ⁇ 10 17 cm ⁇ 3
  • the impurity concentration of the low-resistance buried region 61 is set to 2 ⁇ 10 18 cm ⁇ 3 and the thickness thereof is set as the base. If the thickness of the region 61 is the same, the resistivity of the low-resistance buried region 61 can be reduced to 1/3 of the resistivity of the base region 15.
  • the low resistance buried region 61 can be formed by applying a multi-stage ion implantation method in the manufacturing method of the BJT 10 of the first embodiment described above.
  • a third embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS.
  • the bipolar semiconductor device of the third embodiment is also a BJT. 9, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals.
  • the BJT 10A having the conventional structure has a characteristic that the holes flowing through the base region 15 and the electrons flowing through the collector region 11 are recombined near the base-collector interface.
  • the base region 15 is a region corresponding to the region of the base surface exposed by the etching described above on the lower side (on the high resistance layer 14 side) of the base region 15 formed in layers.
  • a high resistance buried region made of a p-type semiconductor (p ⁇ ) having a higher resistance than the base region 15 or a high resistance buried region 63 made of an n-type semiconductor (n ⁇ ) having a higher resistance than the high resistance layer 14 in contact with the base region 15.
  • the recombination suppression region 16 on the base surface is not formed as in the first embodiment. Other structures are the same as those of the first embodiment.
  • the electron / hole concentration in the high resistance buried region / high resistance layer in the third embodiment is lower than that in the base region / high resistance layer vicinity in the BJT 10A having the conventional structure. Therefore, recombination can be reduced, thereby improving the current amplification factor. Even in the case of the n ⁇ layer, recombination can be suppressed by substantially the same principle, and the current amplification factor can be improved.
  • the impurity concentration of the p-type base region 15 is 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3 , whereas the impurity concentration of the high-resistance buried region 63 is less than or equal to that of the base region 15.
  • the impurity concentration of the p-type base region 15 is, for example, 4 ⁇ 10 17 cm ⁇ 3
  • the impurity concentration of the high-resistance buried region 63 is set to 1 ⁇ 10 17 cm ⁇ 3 or less.
  • a bipolar semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. 11, elements that are substantially the same as those described in FIGS. 7 and 9 are denoted by the same reference numerals.
  • the BJT 300 of the fourth embodiment is configured by combining the characteristic structures of the second and third embodiments.
  • the high resistance buried region 63 is formed so as to be in contact with the lower surface of the low resistance buried region 61.
  • Other configurations are the same as those of the second or third embodiment. The same effect as described above is also exhibited by the BJT 300 of the present embodiment.
  • FIG. 12 A fifth embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIG. 12, elements that are substantially the same as those described in FIGS. 1, 7, and 9 are denoted by the same reference numerals.
  • the BJT 400 of the fifth embodiment is configured by combining the characteristic structures of the first, second and third embodiments.
  • a recombination suppression region 16, a low-resistance buried region 61, and a high-resistance buried region 63 formed so as to be in contact with the lower surface of the low-resistance buried region 61 are provided.
  • Other configurations are the same as those of the first, second, or third embodiment. The same effect as described above is also exhibited by the BJT 400 of the present embodiment.
  • a reverse polarity type in which the polarities of p and n in the description of the process of the manufacturing method are reversed may be used.
  • SiC has been described, but the present invention can also be applied to other semiconductors in which surface recombination is a problem.
  • the present invention relates to a conventional general bipolar silicon carbide semiconductor device having a four-layer structure, which suppresses recombination of electrons of a main current with holes of a control current and improves a current amplification factor, and Even if the base layer is thinned, it is used for improving an increase or variation in the base resistance value, and further used for a method of manufacturing a bipolar silicon carbide semiconductor device having such characteristics.
  • BJT Bipolar semiconductor devices
  • SYMBOLS 11 Collector area
  • region 12 Emitter area
  • region 13 Base contact area
  • region 14 High resistance layer 15
  • region 17 Surface protective film 18
  • Collector electrode 19 Emitter electrode 20
  • Upper layer electrode 40 Substrate 41 High resistance layer 42
  • Base area 43 Low resistance Layer 61 Low resistance buried region 63 High resistance buried region 100 BJT 200 BJT 300 BJT 400 BJT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

Disclosed is a bipolar silicon carbide semiconductor device which is a BJT having a four-layered structure and achieves an improved current amplification factor and a small and stable base resistance by reducing the probability of recombination of electrons and holes and thereby suppressing recombination between a main current and a control current.  The semiconductor device comprises a recombination suppression region (16) having the same conductivity type as and a higher resistivity than a base region (15) or a recombination suppression region (16) having the same conductivity type as and a higher resistivity than an emitter region (12), which is formed near the surface between a base contact region (13) and the emitter region (12).

Description

バイポーラ型炭化珪素半導体装置およびその製造方法Bipolar silicon carbide semiconductor device and manufacturing method thereof
　本発明はバイポーラ型炭化珪素半導体装置およびその製造方法に関し、特に、通常の４層構造を有するバイポーラ型炭化珪素半導体装置であって、主電極間に流れる主電流と制御電極に流れる制御電流との間の再結合を抑制し、電流増幅率を高めるのに適したバイポーラ型炭化珪素半導体装置、およびその製造方法に関する。 The present invention relates to a bipolar silicon carbide semiconductor device and a method for manufacturing the same, and in particular, is a bipolar silicon carbide semiconductor device having a normal four-layer structure, in which a main current flowing between main electrodes and a control current flowing through a control electrode are The present invention relates to a bipolar silicon carbide semiconductor device suitable for suppressing recombination between the two and increasing the current amplification factor, and a method for manufacturing the same.
　炭化珪素（シリコン・カーバイド（Silicon Carbide）、以下では単に「ＳｉＣ」と記す。）は、広く半導体装置に応用されているシリコンと比べて、バンドギャップエネルギが大きいという特性を有する。そのためＳｉＣを利用した半導体装置は、高電圧、大電力、高温動作の条件に適しており、パワーデバイスなどへの適用が期待されている。現在、研究開発されているＳｉＣパワーデバイスの構造は、主に、「ＭＯＳ型」と「接合型」の２つの型に分類されている。 Silicon carbide (Silicon Carbide, hereinafter simply referred to as “SiC”) has a characteristic that the band gap energy is larger than that of silicon widely applied to semiconductor devices. Therefore, a semiconductor device using SiC is suitable for high voltage, high power, and high temperature operation conditions, and is expected to be applied to power devices and the like. The structures of SiC power devices currently being researched and developed are mainly classified into two types, “MOS type” and “junction type”.
　ここでは接合型ＳｉＣパワーデバイスの性能向上という観点で説明する。接合型ＳｉＣパワーデバイスには、静電誘導トランジスタ（Static Induction Transistor、「ＳＩＴ」）や接合型電界効果トランジスタ（Junction Field Effect Transistor、「ＪＦＥＴ」)、あるいはバイポーラトランジスタ（Bipolar Junction Transistor、「ＢＪＴ」）などがある。 Here, it demonstrates from a viewpoint of the performance improvement of a junction type SiC power device. Junction SiC power devices include static induction transistors (Static Induction Transistor, “SIT”), junction field effect transistors (Junction Field Effect Transistor, “JFET”), or bipolar transistors (Bipolar Junction Transistor, “BJT”). and so on.
　従来のＢＪＴの例として例えば非特許文献１に記載された構造を有するものがある。ＢＪＴは、低抵抗のｎ＋型４Ｈ－ＳｉＣ（０００１）面８度オフ基板上に、下側から、ｎ－型高抵抗領域、ｐ型ベース領域、ｎ＋型エミッタ領域の順序に積層されて形成される。エミッタ領域は、多数の細長い形状の領域からなっている。エミッタ領域、ベース領域、コレクタ領域には外部に電気的接続を取るための電極が形成されている。 An example of a conventional BJT is one having a structure described in Non-Patent Document 1, for example. BJT is stacked on the low resistance n + -type 4H-SiC (0001) plane 8 degree off substrate in the order of n − -type high resistance region, p-type base region, and n + -type emitter region from the bottom. It is formed. The emitter region is composed of a number of elongated regions. Electrodes for establishing electrical connection to the outside are formed in the emitter region, base region, and collector region.
　図１３に非特許文献１に開示されたＢＪＴの断面を示している。図１３に示すように、ＢＪＴ５００は、ｎ型低抵抗層であるコレクタ領域５０１、ｎ型高抵抗領域５０２、ｐ型領域のベース領域５０３、ｎ型低抵抗のエミッタ領域５０４、エミッタ領域を囲むように形成されたｐ型低抵抗領域のベースコンタクト領域５０５を備えている。コレクタ領域５０１とベース領域５０３（ベースコンタクト領域５０５）とエミッタ領域のそれぞれの外部には、電気的接続をとるためのコレクタ電極５０６、ベース電極５０７、エミッタ電極５０８が接合されている。さらにＢＪＴ５００の電極以外の露出表面の全体は表面保護膜５０９で覆われている。 FIG. 13 shows a cross section of the BJT disclosed in Non-Patent Document 1. As shown in FIG. 13, the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region. The base contact region 505 of the p-type low resistance region is formed. A collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503 (base contact region 505), and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.
　さらにデバイス特性（電流増幅率）が改善された従来のＢＪＴの例として特許文献１に記載された構造を有するものがある。特許文献１に開示されたＢＪＴは、コレクタ領域となるｎ＋型４Ｈ－ＳｉＣ（０００１）面基板上に、下側から、第１のｎ型高抵抗層、ｐ型ベース領域、第２のｎ型高抵抗層、ｎ＋型エミッタ領域の順序で積層された構造を備えている。当該ＢＪＴで、そのエミッタ領域は、当該積層構造において上面からｎ＋型エミッタ領域、および第２のｎ型高抵抗層の途中まで所定の平面パターン形状でエッチングすることにより、分離されて形成される。ＢＪＴは、その上面に、所定のパターン形状に基づいて分離された複数のエミッタ領域を有している。分離された複数のエミッタ領域の間の領域には、その後にＡｌイオン注入の工程が実行され、ベース領域に接触するｐ型ベースコンタクト領域が形成される。分離された複数のエミッタ領域の各々は、ＢＪＴの平面形状で見てみると、その周囲をベースコンタクト領域で囲まれている。 Further, as an example of a conventional BJT with improved device characteristics (current amplification factor), there is one having a structure described in Patent Document 1. The BJT disclosed in Patent Document 1 has a first n-type high resistance layer, a p-type base region, and a second n-type layer on the n + -type 4H—SiC (0001) surface substrate serving as a collector region from below. A type high resistance layer and an n + type emitter region are stacked in this order. In the BJT, the emitter region is separated and formed by etching in a predetermined planar pattern shape from the upper surface to the middle of the n + -type emitter region and the second n-type high resistance layer in the stacked structure. . The BJT has a plurality of emitter regions separated on the upper surface based on a predetermined pattern shape. In the region between the separated emitter regions, an Al ion implantation process is subsequently performed to form a p-type base contact region in contact with the base region. Each of the plurality of separated emitter regions is surrounded by a base contact region when viewed in a BJT planar shape.
　特許文献１に開示されているＢＪＴは、エミッタ領域とベースコンタクト領域との間において、当該ＢＪＴにおけるＳｉＣ表面を表面再結合抑制半導体層で覆うようにした構造を有している。この表面再結合抑制半導体層は、エミッタ領域から流れ出る電子とベースコンタクト領域から流れ出る正孔との再結合を抑制する機能を有している。これにより、エミッタ領域からの電子とベースコンタクト領域からの正孔の再結合を抑え、接合型半導体層装置の電流増幅率の向上を達成している。 The BJT disclosed in Patent Document 1 has a structure in which the SiC surface of the BJT is covered with a surface recombination suppressing semiconductor layer between the emitter region and the base contact region. The surface recombination suppressing semiconductor layer has a function of suppressing recombination between electrons flowing out from the emitter region and holes flowing out from the base contact region. This suppresses recombination of electrons from the emitter region and holes from the base contact region, and achieves an improvement in the current amplification factor of the junction type semiconductor layer device.
特開２００６－３５１６２１号公報JP 2006-351621 A
　ＢＪＴのごとき接合型トランジスタでは、ベースと呼ばれる制御電極部分がｐｎ接合で形成されている。エミッタとコレクタの間の主電極の間に電流を流すためには、当該制御電極に電流を流す必要がある。主電極の間に流れる電流を「主電流Ｉｃ」、制御電極に流れる電流を「制御電流Ｉｂ」とするとき、両電流の比（Ｉｃ／Ｉｂ）は「電流増幅率」と呼ばれる。ＢＪＴの開発では、電流増幅率の値を大きくすることが重要な課題となっている。 In a junction transistor such as BJT, a control electrode portion called a base is formed by a pn junction. In order to pass a current between the main electrode between the emitter and the collector, it is necessary to pass a current through the control electrode. When the current flowing between the main electrodes is “main current Ic” and the current flowing through the control electrode is “control current Ib”, the ratio of both currents (Ic / Ib) is called “current amplification factor”. In the development of BJT, increasing the value of the current gain is an important issue.
　上記電流増幅率を低下させる要因としては、制御電極から流れ込む正孔（制御電流Ｉｂのキャリア）と主電極間を流れる電子（主電流Ｉｃのキャリア）との再結合を挙げることができる。再結合電流の値は、電子密度、正孔密度、再結合準位密度に依存し、それぞれの密度が高いほど再結合電流も大きくなる。 As a factor for lowering the current amplification factor, recombination of holes flowing from the control electrode (carrier of the control current Ib) and electrons flowing between the main electrodes (carrier of the main current Ic) can be mentioned. The value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.
　再結合が発生しやすい部位としてはＳｉＣ表面が知られている。ＳｉＣ表面の再結合準位の密度を低減するために、ＳｉＣ表面を酸化して保護膜を形成するプロセスで各種の工夫をなすことが提案されている。この点は特許文献１にも記載されている。さらに特許文献１のＢＪＴでは、再結合確率を下げるために、ＳｉＣ表面に、濃度の低いｐ型領域からなる表面再結合抑制半導体層を設けるようにしている。このような表面再結合抑制半導体層を形成すると、ＳｉＣ表面に電子に対する電位障壁が形成されるので、ＳｉＣ表面での電子密度を下げることができる。さらに、濃度の低いｐ型領域でＳｉＣ表面に高抵抗層を形成することにより、正孔の密度も低く抑えることができる。かかる表面再結合抑制半導体層を形成することにより、接合型トランジスタのＳｉＣ表面に再結合準位が存在したとしても、再結合確率を低減することができ、接合型トランジスタの電流増幅率を大きくすることができる。 The SiC surface is known as a site where recombination is likely to occur. In order to reduce the density of recombination levels on the SiC surface, various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1. Further, in BJT of Patent Document 1, in order to reduce the recombination probability, a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface. When such a surface recombination-inhibiting semiconductor layer is formed, a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered. Furthermore, the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration. By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.
　以上のようにＢＪＴにおいて、ＳｉＣ表面での再結合を抑制して電流増幅率を大きくする試みが多くなされている。 As described above, in BJT, many attempts have been made to increase the current amplification factor by suppressing recombination on the SiC surface.
　他方、上面側からエミッタ領域、ベース領域、高抵抗層、および基板（コレクタ領域）の順序で構成される４層構造を有した従来の一般的なＢＪＴでは、今まで、上記のような再結合を抑制して高い電流増幅率を実現する試みが十分になされていなかった。かかる一般的なＢＪＴでも、制御電極から流れ込む正孔と主電極間を流れる電子とが、ＳｉＣ表面に多数存在する再結合中心を介して再結合することが電流増幅率を下げる要因となる。またベース領域とコレクタ領域等との界面でも電子と正孔の濃度が共に高いため、再結合が盛んに発生するという問題もある。またＢＪＴの製造方法では、エミッタ領域をベース領域の表面が露出するまでエッチングするが、その際にベース領域の層をわずかに削る必要がある。このため、ベース領域が薄くなるので抵抗が増大し、エッチングの基板面内のばらつきによりベース抵抗がばらつくことになる。ＢＪＴの電流増幅率を向上させるためにはベース領域の厚みを薄くすることが望ましいが、ベース領域の厚みを薄くすると、前述したエミッタ領域のエッチングプロセスに起因するベース抵抗の増大やばらつきが顕著になる。４層構造を有する従来のＢＪＴについて、高い電流増幅率と、小さく安定したベース抵抗とを両立するデバイスは実現されていない。 On the other hand, in the conventional general BJT having a four-layer structure composed of an emitter region, a base region, a high-resistance layer, and a substrate (collector region) in this order from the upper surface side, recombination as described above has been performed so far. There has not been a sufficient attempt to realize a high current amplification factor by suppressing the above. Even in such a general BJT, the recombination of holes flowing from the control electrode and electrons flowing between the main electrodes via recombination centers existing on the SiC surface causes a reduction in current amplification factor. Another problem is that recombination occurs frequently because both the electron and hole concentrations are high at the interface between the base region and the collector region. In the BJT manufacturing method, the emitter region is etched until the surface of the base region is exposed. At this time, the base region layer needs to be slightly shaved. For this reason, since the base region becomes thin, the resistance increases, and the base resistance varies due to variations in the etching substrate surface. In order to improve the current amplification factor of the BJT, it is desirable to reduce the thickness of the base region. However, if the thickness of the base region is reduced, the increase or variation in the base resistance due to the above-described etching process of the emitter region becomes remarkable. Become. For a conventional BJT having a four-layer structure, a device that achieves both a high current gain and a small and stable base resistance has not been realized.
　本発明の目的は、上記の問題を鑑み、４層構造を有する従来の一般的なＢＪＴで、電子と正孔の再結合確率を低減し、主電極間に流れる主電流と制御電極に流れる制御電流との間の再結合を抑制し、電流増幅率を向上することができ、小さく安定したベース抵抗を実現することができるバイポーラ型炭化珪素半導体装置およびその製造方法を提供することにある。 In view of the above problems, an object of the present invention is a conventional BJT having a four-layer structure, which reduces the recombination probability of electrons and holes, and controls the main current flowing between the main electrodes and the control electrode. An object of the present invention is to provide a bipolar silicon carbide semiconductor device capable of suppressing recombination between currents, improving a current amplification factor, and realizing a small and stable base resistance, and a method for manufacturing the same.
　第１のバイポーラ型炭化珪素半導体装置（請求項１に対応）は、炭化珪素半導体結晶で作られた基板であるコレクタ領域と、コレクタ領域の上に形成された高抵抗層と、高抵抗層の上に形成されたベース領域と、低抵抗層からなり、ベース領域と接合されるエミッタ領域と、エミッタ領域の周囲に形成され、ベース領域に接合する低抵抗のベースコンタクト領域と、ベースコンタクト領域とエミッタ領域との間の表面付近に、ベース領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域、またはエミッタ領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域と、を有することで特徴づけられる。 A first bipolar silicon carbide semiconductor device (corresponding to claim 1) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer. A base region formed thereon, an emitter region formed of a low-resistance layer and bonded to the base region; a low-resistance base contact region formed around the emitter region and bonded to the base region; and a base contact region Near the surface between the emitter region, a recombination suppression region having the same conductivity type as the base region and higher than its resistivity, or a recombination suppression region having the same conductivity type as the emitter region and higher than its resistivity It is characterized by having.
　第２のバイポーラ型炭化珪素半導体装置（請求項２に対応）は、炭化珪素半導体結晶で作られた基板であるコレクタ領域と、コレクタ領域の上に形成された高抵抗層と、高抵抗層の上に形成されたベース領域と、低抵抗層からなり、ベース領域と接合されるエミッタ領域と、エミッタ領域の周囲に形成され、ベース領域に接合する低抵抗のベースコンタクト領域と、ベース領域に、ベースコンタクト領域に接すると共に、ベース領域と同じ導電型でありかつその抵抗率と同等かまたは当該抵抗率よりも低い埋め込み領域と、を有することで特徴づけられる。 A second bipolar silicon carbide semiconductor device (corresponding to claim 2) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer. The base region formed above, an emitter region composed of a low resistance layer, joined to the base region, a low resistance base contact region formed around the emitter region and joined to the base region, and the base region, It is characterized by having a buried region that is in contact with the base contact region and has the same conductivity type as the base region and has a resistivity equal to or lower than the resistivity.
　第３のバイポーラ型炭化珪素半導体装置（請求項３に対応）は、炭化珪素半導体結晶で作られた基板であるコレクタ領域と、コレクタ領域の上に形成された高抵抗層と、高抵抗層の上に形成されたベース領域と、低抵抗層からなり、ベース領域と接合されるエミッタ領域と、エミッタ領域の周囲に形成され、ベース領域に接合する低抵抗のベースコンタクト領域と、高抵抗層に、ベース領域に接すると共に、ベース領域と同じ導電型でありかつその抵抗率よりも高い埋め込み領域、または前記高抵抗領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域と、を有することで特徴づけられる。 A third bipolar silicon carbide semiconductor device (corresponding to claim 3) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer. A base region formed on the base region, an emitter region joined to the base region, a low resistance base contact region formed around the emitter region and joined to the base region, and a high resistance layer A buried region that is in contact with the base region and has the same conductivity type as that of the base region and has a resistivity higher than that of the base region, or a recombination suppression region that has the same conductivity type as that of the high resistance region and has a resistivity higher than that of the base region. It is characterized by having.
　第４のバイポーラ型炭化珪素半導体装置（請求項４に対応）は、上記の構成において、コレクタ領域は第１の導電型の低抵抗層であり、エミッタ領域は第１の導電型の低抵抗層であり、高抵抗層は第１の導電型であり、ベース領域は第２の導電型であることを特徴とする。 In the fourth bipolar silicon carbide semiconductor device (corresponding to claim 4), the collector region is a low-resistance layer of the first conductivity type and the emitter region is a low-resistance layer of the first conductivity type in the above configuration. The high resistance layer is of the first conductivity type, and the base region is of the second conductivity type.
　第１のバイポーラ型炭化珪素半導体装置の製造方法（請求項５に対応）は、炭化珪素の半導体結晶で作られかつコレクタ領域となる基板の上に高抵抗層を形成する第１の工程と、高抵抗層の上にベース領域を形成する第２の工程と、ベース領域の上に低抵抗層を形成するための第３の工程と、低抵抗層を部分的にエッチングしてエミッタ領域を形成する第４の工程と、エッチングにより露出したベース領域の表面付近に、ベース領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域、またはエミッタ領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域を形成する第５の工程と、ベース領域に接合するベースコンタクト領域を形成する第６の工程と、を含む方法である。 A first bipolar silicon carbide semiconductor device manufacturing method (corresponding to claim 5) includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer In the fourth step, a recombination suppression region having the same conductivity type as the base region and higher in resistivity than the base region exposed by etching, or having the same conductivity type as the emitter region and its resistance A fifth step of forming a recombination suppression region higher than the rate, and a sixth step of forming a base contact region bonded to the base region.
　第２のバイポーラ型炭化珪素半導体装置の製造方法（請求項６に対応）は、炭化珪素の半導体結晶で作られかつコレクタ領域となる基板の上に高抵抗層を形成する第１の工程と、高抵抗層の上にベース領域を形成する第２の工程と、ベース領域の上に低抵抗層を形成するための第３の工程と、低抵抗層を部分的にエッチングしてエミッタ領域を形成する第４の工程と、ベース領域に、ベースコンタクト領域に接すると共に、ベース領域と同じ導電型でありかつその抵抗率と同等かまたは当該抵抗率よりも低い埋め込み領域を形成する第５の工程と、ベース領域に接合するベースコンタクト領域を形成する第６の工程と、を含む方法である。 A second bipolar silicon carbide semiconductor device manufacturing method (corresponding to claim 6) includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer And a fifth step of forming a buried region in the base region in contact with the base contact region and having the same conductivity type as the base region and having a resistivity equal to or lower than the resistivity. And a sixth step of forming a base contact region bonded to the base region.
　第３のバイポーラ型炭化珪素半導体装置の製造方法（請求項７に対応）は、炭化珪素の半導体結晶で作られかつコレクタ領域となる基板の上に高抵抗層を形成する第１の工程と、高抵抗層の上にベース領域を形成する第２の工程と、ベース領域の上に低抵抗層を形成するための第３の工程と、低抵抗層を部分的にエッチングしてエミッタ領域を形成する第４の工程と、高抵抗層に、ベース領域に接すると共に、ベース領域と同じ導電型でありかつその抵抗率よりも高い埋め込み領域、またはエミッタ領域と同じ導電型でありかつその抵抗率よりも高い埋め込み領域を形成する第５の工程と、ベース領域に接合するベースコンタクト領域を形成する第６の工程と、を含む方法である。 A third bipolar silicon carbide semiconductor device manufacturing method (corresponding to claim 7) includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer And a fourth step of contacting the base region with the high-resistance layer and having the same conductivity type as that of the base region and higher than its resistivity, or having the same conductivity type as that of the emitter region and the resistivity thereof. A fifth step of forming a higher buried region and a sixth step of forming a base contact region bonded to the base region.
　第４のバイポーラ型炭化珪素半導体装置の製造方法（請求項８に対応）は、上記の方法において、コレクタ領域、エミッタ領域、およびベースコンタクト領域のそれぞれに、コレクタ電極、エミッタ電極、ベース電極を形成する工程と、エミッタ電極とベース電極の上側に上層電極を形成する工程と、を有することを特徴とする。 According to a fourth bipolar silicon carbide semiconductor device manufacturing method (corresponding to claim 8), in the above method, a collector electrode, an emitter electrode, and a base electrode are formed in each of the collector region, the emitter region, and the base contact region. And a step of forming an upper layer electrode above the emitter electrode and the base electrode.
　本発明に係るバイポーラ型炭化珪素半導体装置によれば、次の効果を奏する。
　第１に、ベース領域からエミッタ領域にかけてベース表面で再結合抑制領域を形成したため、炭化珪素半導体の表面に形成された再結合準位に電子または正孔を近づけることを防止して電流増幅率を高めることができる。 The bipolar silicon carbide semiconductor device according to the present invention has the following effects.
First, since the recombination suppression region is formed on the base surface from the base region to the emitter region, it prevents the electron or hole from approaching the recombination level formed on the surface of the silicon carbide semiconductor, thereby increasing the current amplification factor. Can be increased.
　第２に、またベース領域内に当該ベース領域よりも低抵抗の埋め込み領域を形成したため、ベースコンタクト領域からの正孔が埋め込み領域に流れ込むことによって炭化珪素半導体の表面での再結合を防止し、電流増幅率を高めることができる。 Second, since a buried region having a lower resistance than that of the base region is formed in the base region, holes from the base contact region flow into the buried region to prevent recombination on the surface of the silicon carbide semiconductor, The current amplification factor can be increased.
　第３に、高抵抗層に、ベース領域あるいは高抵抗層よりも高い抵抗の埋め込み領域を形成したため、高抵抗層からの電子がベース領域に近づくことを防止し、電流増幅率を高めることができる。 Third, since the base region or the buried region having a higher resistance than the high resistance layer is formed in the high resistance layer, electrons from the high resistance layer can be prevented from approaching the base region, and the current amplification factor can be increased. .
　第４に、上記のごとく所要の箇所に再結合抑制領域あるいは低抵抗または高抵抗の埋め込み領域を設けることにより、ベース抵抗値を低減できると共にばらつきを抑えることができ、ＢＪＴのデバイス特性を均一化することができる。 Fourth, by providing a recombination suppression region or a low-resistance or high-resistance buried region at a required location as described above, the base resistance value can be reduced and variations can be suppressed, and the device characteristics of BJT can be made uniform. can do.
　また本発明に係るバイポーラ型炭化珪素半導体装置の製造方法によれば、バイポーラ型炭化珪素半導体装置において上記のごとく所要の箇所に層状の再結合抑制半導体領域を設けるようにしたため、エミッタから流れ込む電子とベースから流れ込む正孔の再結合を抑制することができ、高い電流増幅率を有するバイポーラ型炭化珪素半導体装置を容易にかつ確実に製作することができる。 According to the method for manufacturing a bipolar silicon carbide semiconductor device according to the present invention, the bipolar silicon carbide semiconductor device is provided with the layered recombination suppressing semiconductor region at a required location as described above, and therefore, electrons flowing from the emitter and Recombination of holes flowing from the base can be suppressed, and a bipolar silicon carbide semiconductor device having a high current gain can be easily and reliably manufactured.
本発明の第１実施例によるバイポーラ型半導体装置（ＢＪＴ）の部分縦断面図であり、図２のＡ－Ａ線による拡大断面図である。FIG. 3 is a partial longitudinal sectional view of a bipolar semiconductor device (BJT) according to a first embodiment of the present invention, and is an enlarged sectional view taken along line AA of FIG. 第１実施例によるバイポーラ型半導体装置の一部の平面図である。1 is a plan view of a part of a bipolar semiconductor device according to a first embodiment. 従来のバイポーラ型半導体装置の動作の問題を説明する部分縦断面図である。It is a fragmentary longitudinal cross-section explaining the problem of operation | movement of the conventional bipolar type semiconductor device. 第１実施例によるバイポーラ型半導体装置の動作を説明する部分縦断面図である。It is a fragmentary longitudinal cross-sectional view explaining the operation | movement of the bipolar type semiconductor device by 1st Example. 第１実施例によるバイポーラ型半導体装置の製造方法を説明するフローチャートである。3 is a flowchart illustrating a method for manufacturing a bipolar semiconductor device according to the first embodiment. 第１実施例によるバイポーラ型半導体装置の製造方法の各プロセスに対応するデバイス構造を示す部分縦断面図である。It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the bipolar type semiconductor device by 1st Example. 第１実施例によるバイポーラ型半導体装置の製造方法の各プロセスに対応するデバイス構造を示す部分縦断面図である。It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the bipolar type semiconductor device by 1st Example. 本発明の第２実施例によるバイポーラ型半導体装置の部分縦断面図である。FIG. 5 is a partial longitudinal sectional view of a bipolar semiconductor device according to a second embodiment of the present invention. 第２実施例のバイポーラ型半導体装置の動作を説明する部分縦断面図である。It is a fragmentary longitudinal cross-sectional view explaining operation | movement of the bipolar type semiconductor device of 2nd Example. 本発明の第３実施例によるバイポーラ型半導体装置の縦断面図である。It is a longitudinal cross-sectional view of the bipolar type semiconductor device by 3rd Example of this invention. 第３実施例のバイポーラ型半導体装置の動作を説明する縦断面図である。It is a longitudinal cross-sectional view explaining the operation | movement of the bipolar type semiconductor device of 3rd Example. 本発明の第４実施例によるバイポーラ型半導体装置の縦断面図である。FIG. 6 is a longitudinal sectional view of a bipolar semiconductor device according to a fourth embodiment of the present invention. 本発明の第５実施例によるバイポーラ型半導体装置の縦断面図である。FIG. 6 is a longitudinal sectional view of a bipolar semiconductor device according to a fifth embodiment of the present invention. 従来のバイポーラ型半導体装置の構造を示した縦断面図である。It is the longitudinal cross-sectional view which showed the structure of the conventional bipolar type semiconductor device.
　以下に、本発明の好適な幾つかの実施例について、添付図面に基づいて詳細に説明する。 Hereinafter, some preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
　＜第１実施例＞
　図１～図６Ｂを参照して本発明によるバイポーラ型半導体装置の第１の実施例を説明する。このバイポーラ型半導体装置は従来の一般的な４層構造のＢＪＴの例を示している。 <First embodiment>
A first embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS. 1 to 6B. This bipolar semiconductor device shows an example of a conventional BJT having a general four-layer structure.
　図２に示すように、ＢＪＴ１０は、そのデバイス上面の特定な単位領域に、並列に配列された例えば５本のエミッタ電極１９を備えている。これらのエミッタ電極１９はベース電極２０によって囲まれている。 As shown in FIG. 2, the BJT 10 includes, for example, five emitter electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device. These emitter electrodes 19 are surrounded by a base electrode 20.
　図１に示す縦断面構造において、ＢＪＴ１０は、ＳｉＣ（炭化珪素）結晶を有する下側面部分に形成されたｎ型の低抵抗層（ｎ＋層）からなるコレクタ領域１１と、当該ＳｉＣ結晶を有する上側面部分に形成されたｎ型の低抵抗層（ｎ＋層）からなるエミッタ領域１２を備えている。コレクタ領域１１を形成する層が基板となっている。 In the longitudinal cross-sectional structure shown in FIG. 1, the BJT 10 has a collector region 11 formed of an n-type low resistance layer (n + layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal. An emitter region 12 made of an n-type low resistance layer (n + layer) formed on the upper side surface portion is provided. A layer forming the collector region 11 is a substrate.
　図２の平面図の位置関係において、複数のエミッタ電極１９の各々の周囲には、当該エミッタ電極１９を囲むようにベース電極２０が形成されている。この意味は、エミッタ電極１９の下側に位置するエミッタ領域１２の周囲は、ベース電極２０の下側に位置するｐ型のベースコンタクト領域１３によって囲まれているということである。ベースコンタクト領域１３は所定の深さ位置まで形成されている。さらにＢＪＴ１０において、上側のエミッタ領域１２と下側のコレクタ領域１１の間には、下側からｎ型高抵抗層（ｎ－層）１４とｐ型のベース領域１５とが積層されて形成されている。ベース領域１５は、ベースコンタクト領域１３と接触して電気的に接続されるように形成されている。換言すれば、ベースコンタクト領域１３は、ベース領域１５上の所定の位置に埋め込むように形成されている。 In the positional relationship of the plan view of FIG. 2, a base electrode 20 is formed around each of the plurality of emitter electrodes 19 so as to surround the emitter electrode 19. This means that the periphery of the emitter region 12 located below the emitter electrode 19 is surrounded by the p-type base contact region 13 located below the base electrode 20. The base contact region 13 is formed up to a predetermined depth position. In addition BJT 10, between the upper emitter region 12 and a lower collector region 11, n-type high-resistance layer from the lower side (n - layer) and 14 and p-type base region 15 is formed by stacking Yes. The base region 15 is formed so as to be in contact with and electrically connected to the base contact region 13. In other words, the base contact region 13 is formed so as to be embedded at a predetermined position on the base region 15.
　本実施例において、上記の「ｎ型」は「第１の導電型」であり、上記の「ｐ型」は「第２の導電型」であるとする。 In this embodiment, it is assumed that the “n-type” is “first conductivity type” and the “p-type” is “second conductivity type”.
　本実施例のＢＪＴ１０では、さらに、層状のｐ型ベース領域１５の表面の一部に形成されたｐ＋型のベースコンタクト領域１３と、エミッタ領域１２との間において、当該ｐ型ベース領域１５の露出表面部分に当該表面部分を覆うようにした層状の再結合抑制領域１６とを設けている。再結合抑制領域１６の深さはベースコンタクト領域１３の深さとほぼ等しい。上記の再結合抑制領域１６は、高抵抗の半導体であり「ｐ－」または「ｎ－」である。ベースコンタクト領域１３はベース領域１５の表面からに接触し、さらに表面より当該ベース領域１５の内部に侵入するように形成されている。 In the BJT 10 of this embodiment, the p + type base region 15 is further interposed between the p + type base contact region 13 formed on a part of the surface of the layered p type base region 15 and the emitter region 12. A layered recombination suppression region 16 is provided on the exposed surface portion so as to cover the surface portion. The depth of the recombination suppression region 16 is substantially equal to the depth of the base contact region 13. The recombination suppression region 16 is a high-resistance semiconductor and is “p − ” or “n − ”. The base contact region 13 is formed so as to come into contact with the surface of the base region 15 and further enter the inside of the base region 15 from the surface.
　上記のＢＪＴ１０の構造において、図１に示すように、コレクタ領域１１の下側表面にはコレクタ電極１８が接合され、エミッタ領域１２の上側表面にはエミッタ電極１９が接合され、ベースコンタクト領域１３の上側表面にはベース電極２０が接合されている。ＢＪＴ１０の上面において、エミッタ電極１９とベース電極２０の間における露出表面は、表面保護膜１７によって覆われており、これにより保護されている。 In the structure of the BJT 10 described above, as shown in FIG. 1, the collector electrode 18 is bonded to the lower surface of the collector region 11, the emitter electrode 19 is bonded to the upper surface of the emitter region 12, and the base contact region 13 A base electrode 20 is joined to the upper surface. On the upper surface of the BJT 10, the exposed surface between the emitter electrode 19 and the base electrode 20 is covered with a surface protective film 17 and is protected thereby.
　図２に示すように、エミッタ電極１９およびベース電極２０の各々の上側には上層電極２１が設けられている。図１において、上層電極２１の図示は省略されている。 As shown in FIG. 2, an upper layer electrode 21 is provided above each of the emitter electrode 19 and the base electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.
　上記ＢＪＴ１０において、主電流は、エミッタ領域１２（またはエミッタ電極１９）からコレクタ領域１１（またはコレクタ電極１８）に流れる電子流である。エミッタ領域１２とコレクタ領域１１は主電流を流すための主電極用領域である。主電流の通電（オン）と非通電（オフ）は、ベース電極２０に印加されるベース電圧、すなわち、ベースコンタクト領域１３およびベース領域１５とエミッタ領域１２との間に加えられる制御信号に基づいて制御される。ベース・エミッタ間の印加電圧が０Ｖ以下であるときにはＢＪＴ１０は主電流が流れず、オフ状態になる。ベース・エミッタ間に一定以上の電圧が印加されると、ＢＪＴ１０は主電流が流れてオン状態に移行する。また、オン状態では、ベース領域１５とエミッタ領域１２の間に形成されているｐｎ接合が順バイアスされて、ベース領域１５からエミッタ領域１２に制御電流である正孔電流が流れる。 In the BJT 10, the main current is an electron flow that flows from the emitter region 12 (or the emitter electrode 19) to the collector region 11 (or the collector electrode 18). The emitter region 12 and the collector region 11 are main electrode regions for flowing a main current. Energization (ON) and non-energization (OFF) of the main current are based on a base voltage applied to the base electrode 20, that is, a control signal applied between the base contact region 13 and the base region 15 and the emitter region 12. Be controlled. When the applied voltage between the base and the emitter is 0 V or less, the BJT 10 does not flow main current and is turned off. When a voltage of a certain level or higher is applied between the base and the emitter, the BJT 10 is turned on due to the main current flowing. In the ON state, the pn junction formed between the base region 15 and the emitter region 12 is forward-biased, and a hole current that is a control current flows from the base region 15 to the emitter region 12.
　図３と図４を参照し、従来のＢＪＴ構造と本実施例のＢＪＴ構造とを対比しながら、ＢＪＴ１０の特徴的構造を説明する。 3 and 4, the characteristic structure of the BJT 10 will be described while comparing the conventional BJT structure with the BJT structure of the present embodiment.
　図３は従来の構造を有するＢＪＴ１０Ａを示す。図３において、上記の図１で説明した要素と同一の要素には同一の符号を付している。ＢＪＴ１０Ａの構造では、ベース領域１５において、ベースコンタクト領域１３とエミッタ領域１２との間のＳｉＣ表面の近傍領域には多数の再結合準位２２が形成されている。このため、エミッタ領域１２からコレクタ領域１１に向かって流れる主電流Ｉ１の一部の電子２３と、ベースコンタクト領域１３から流れ込む正孔２４とが再結合準位２２の箇所で再結合する。このような電子２３と正孔２４との再結合は、ベース領域１５と高抵抗層１４等との界面でも盛んに発生する。以上の結果、ＢＪＴ１０Ａの動作に寄与しない無効なベース電流が流れ、ＢＪＴ１０Ａの電流増幅率を低下させる。 FIG. 3 shows a BJT 10A having a conventional structure. In FIG. 3, the same elements as those described in FIG. In the structure of the BJT 10A, in the base region 15, a large number of recombination levels 22 are formed in the vicinity of the SiC surface between the base contact region 13 and the emitter region 12. Therefore, some of the electrons 23 of the main current I1 flowing from the emitter region 12 toward the collector region 11 and the holes 24 flowing from the base contact region 13 are recombined at the recombination level 22. Such recombination of electrons 23 and holes 24 occurs frequently at the interface between the base region 15 and the high resistance layer 14. As a result, an invalid base current that does not contribute to the operation of the BJT 10A flows, and the current amplification factor of the BJT 10A is reduced.
　従来構造を有するＢＪＴ１０Ａに対して、本実施例のＢＪＴ１０では、図４に示すように、ベースコンタクト領域１３とエミッタ領域１２との間で露出するベース領域１５の表面およびその近傍部分に層状の再結合抑制領域１６が形成される。再結合抑制領域１６は「ｐ－」または「ｎ－」の半導体領域で形成されており、電子２３または正孔２４に対して高い電位障壁を形成するとともに正孔または電子濃度の低い高抵抗層となっているとなっている。この再結合抑制領域１６が存在することによって、ベースコンタクト領域１３からベース領域１５に流れる正孔２４は図４中再結合抑制領域１６には流れにくく主に表面以外のベース領域１５を流れ、エミッタ領域１２から流れ込む電子もＳｉＣ表面付近は流れにくくなる。その結果、図４に示すように、エミッタ領域１２から流れ出す電子２３は、正孔と再結合することなく主電流Ｉ２としてコレクタ領域１１の方向に向かって流れ、ＢＪＴ１０の電流増幅率を向上させることができる。 In contrast to the BJT 10A having the conventional structure, in the BJT 10 of the present embodiment, as shown in FIG. 4, a layer-like layer is formed on the surface of the base region 15 exposed between the base contact region 13 and the emitter region 12 and its vicinity. A coupling suppression region 16 is formed. The recombination suppressing region 16 is formed of a “p − ” or “n − ” semiconductor region, and forms a high potential barrier against the electrons 23 or the holes 24 and also has a high resistance layer having a low hole or electron concentration. It has become. Due to the existence of the recombination suppression region 16, holes 24 flowing from the base contact region 13 to the base region 15 do not easily flow into the recombination suppression region 16 in FIG. Electrons flowing from the region 12 are also difficult to flow near the SiC surface. As a result, as shown in FIG. 4, the electrons 23 flowing out from the emitter region 12 flow toward the collector region 11 as the main current I2 without recombining with the holes, thereby improving the current amplification factor of the BJT 10. Can do.
　再結合抑制領域１６を形成する際、ベースコンタクト領域１３を作る場合と同様に、イオン注入法を用いる。この場合、ベースコンタクト領域１３を作るときのイオン注入に比較して注入濃度が極めて低く、イオン注入に要するエネルギも低い。そのため再結合抑制領域１６を形成するためのイオン注入では再結合準位の密度を低く抑えることができる。 When forming the recombination suppression region 16, an ion implantation method is used as in the case of forming the base contact region 13. In this case, the implantation concentration is extremely low and the energy required for ion implantation is low compared to the ion implantation for forming the base contact region 13. Therefore, in the ion implantation for forming the recombination suppression region 16, the density of recombination levels can be suppressed low.
　ここで、第１実施例のＢＪＴ１０の各高抵抗層等の不純物濃度および寸法について具体的な一例を説明する。 Here, a specific example of the impurity concentration and dimensions of each high resistance layer of the BJT 10 of the first embodiment will be described.
　ＢＪＴ１０は、例えば阻止電圧６００Ｖを目標に設計されている。基板の部分には、（０００１）面から８度オフさせた低抵抗のｎ型４Ｈ－ＳｉＣ基板を使用している。ＢＪＴ１０において、当該基板部分がコレクタ領域１１となる。基板上のｎ型高抵抗層１４は、エミッタ・コレクタ間に加わる高電圧を阻止するための層である。本実施例では、高抵抗層１４は、６００Ｖ以上の電圧を阻止するように、例えば、厚み１０μｍ、不純物濃度１×１０１６ｃｍ－３に設定されている。高抵抗層１４上のｐ型のベース領域１５は、エミッタ・コレクタ間に高電圧が印加されたときに、空乏化しないようにその厚みと不純物濃度が設定されている。本実施形態では、ｐ型ベース領域１５は、厚み０．２～０．５μｍ、不純物濃度４×１０１７～２×１０１８ｃｍ－３程度が用いられる。ベース領域１５上には、厚さ０．５～２．０μｍ、不純物濃度１～５×１０１９ｃｍ－３の低抵抗のｎ型エミッタ領域１２が設けられている。エミッタ領域１２の周囲には、低抵抗のベースコンタクト領域１３が形成されている。図２に示すように、エミッタ領域１２の平面形状は、細長い島状の形状である。１つのＢＪＴ１０に複数のエミッタ領域１２を備えている。１つのエミッタ領域１２の寸法は、幅３～１０μｍ、長さ１００～１０００μｍ程度である。ベースコンタクト領域１３とエミッタ領域１２を含めた単位構造の周期は約１０～３０μｍである。 The BJT 10 is designed with a target of a blocking voltage of 600V, for example. As the substrate portion, a low resistance n-type 4H—SiC substrate turned off by 8 degrees from the (0001) plane is used. In the BJT 10, the substrate portion becomes the collector region 11. The n-type high resistance layer 14 on the substrate is a layer for blocking a high voltage applied between the emitter and the collector. In the present embodiment, the high resistance layer 14 is set to have a thickness of 10 μm and an impurity concentration of 1 × 10 16 cm −3 , for example, so as to block a voltage of 600 V or higher. The p-type base region 15 on the high resistance layer 14 has a thickness and an impurity concentration so as not to be depleted when a high voltage is applied between the emitter and the collector. In this embodiment, the p-type base region 15 has a thickness of 0.2 to 0.5 μm and an impurity concentration of about 4 × 10 17 to 2 × 10 18 cm −3 . On the base region 15, a low resistance n-type emitter region 12 having a thickness of 0.5 to 2.0 μm and an impurity concentration of 1 to 5 × 10 19 cm −3 is provided. A low-resistance base contact region 13 is formed around the emitter region 12. As shown in FIG. 2, the planar shape of the emitter region 12 is an elongated island shape. One BJT 10 includes a plurality of emitter regions 12. The dimensions of one emitter region 12 are about 3 to 10 μm in width and about 100 to 1000 μm in length. The period of the unit structure including the base contact region 13 and the emitter region 12 is about 10 to 30 μm.
　次に、図５，６Ａ，６Ｂを参照してＢＪＴ１０の製造方法を説明する。図５は製造方法の各プロセスを示すフローチャートである。図６Ａと図６Ｂは各プロセスで製作される構造を示す縦断面図である。 Next, a method for manufacturing the BJT 10 will be described with reference to FIGS. FIG. 5 is a flowchart showing each process of the manufacturing method. 6A and 6B are longitudinal sectional views showing structures manufactured by each process.
　ＢＪＴ１０の製造方法は、次のプロセス（１）～（１０）（ステップＳ１１～Ｓ２０）から成っている。図５に示されるようにステップＳ１１からステップＳ２０に到る順序で各プロセスが実行される。 The manufacturing method of the BJT 10 includes the following processes (1) to (10) (steps S11 to S20). As shown in FIG. 5, each process is executed in the order from step S11 to step S20.
　（１）高抵抗層形成プロセス（ステップＳ１１）
　（２）ベース領域形成プロセス（ステップＳ１２）
　（３）低抵抗層形成プロセス（ステップＳ１３）
　（４）エミッタエッチングプロセス（ステップＳ１４）
　（５）再結合抑制領域形成プロセス（ステップＳ１５）
　（６）ベースコンタクト領域形成プロセス（ステップ１６）
　（７）イオン注入層活性化プロセス（ステップＳ１７）
　（８）表面保護膜形成プロセス（ステップＳ１８）
　（９）電極形成プロセス（ステップＳ１９）
　（１０）上層電極形成プロセス（ステップＳ２０） (1) High resistance layer forming process (step S11)
(2) Base region formation process (step S12)
(3) Low resistance layer formation process (step S13)
(4) Emitter etching process (step S14)
(5) Recombination suppression region formation process (step S15)
(6) Base contact region formation process (step 16)
(7) Ion implantation layer activation process (step S17)
(8) Surface protective film formation process (step S18)
(9) Electrode formation process (step S19)
(10) Upper layer electrode formation process (step S20)
　上記のステップＳ１１～Ｓ１３を実施することによって図６Ａの（ａ）に示される構造が形成される。 The structure shown in (a) of FIG. 6A is formed by performing the above steps S11 to S13.
　ｎ型高抵抗層形成プロセス（ステップＳ１１）では、ＳｉＣで形成されたｎ型基板４０の上に、エピタキシャル成長法により、厚さ１０μｍで、濃度１×１０１６ｃｍ－３の窒素を不純物としてドープした高抵抗層４１を成長させる。基板４０には「４Ｈ－ＳｉＣ（0001）８°off」が用いられている。また基板４０は、前述したｎ型低抵抗層のコレクタ領域１１となる。 In the n-type high resistance layer forming process (step S11), nitrogen having a thickness of 10 μm and a concentration of 1 × 10 16 cm −3 is doped as an impurity on the n-type substrate 40 formed of SiC by an epitaxial growth method. A high resistance layer 41 is grown. “4H—SiC (0001) 8 ° off” is used for the substrate 40. The substrate 40 becomes the collector region 11 of the n-type low resistance layer described above.
　ベース領域形成プロセス（ステップＳ１２）では、ｎ型高抵抗層４１の上に、エピタキシャル成長法により、アルミニウム（Ａｌ）を不純物として４×１０１７～２×１０１８ｃｍ－３の濃度で０．２～０．５μｍのｐ型のベース領域４２を成長させる。 In the base region formation process (step S12), an epitaxial growth method is performed on the n-type high resistance layer 41 with aluminum (Al) as an impurity at a concentration of 4 × 10 17 to 2 × 10 18 cm −3 to 0.2 to A 0.5 μm p-type base region 42 is grown.
　低抵抗層形成プロセス（ステップＳ１３）では、ｎ型のベース領域４２の上に、エピタキシャル成長法により、厚さ０．５～２．０μｍで濃度１～５×１０１９ｃｍ－３の窒素を不純物としてドープしたｎ型の低抵抗層４３を成長させる。この低抵抗層４３は、前述したエミッタ領域１２を形成する部分である。 In the low resistance layer formation process (step S13), nitrogen having a thickness of 0.5 to 2.0 μm and a concentration of 1 to 5 × 10 19 cm −3 is formed as an impurity on the n-type base region 42 by an epitaxial growth method. A doped n-type low resistance layer 43 is grown. The low resistance layer 43 is a portion for forming the emitter region 12 described above.
　次のエミッタエッチングプロセス（ステップＳ１４）では、図６Ａの（ａ）に示された構造において、その上面に、ＣＶＤ法によりシリコン酸化膜５１を堆積させ、フォトリソグラフィーを行い、その後にＲＩＥによりシリコン酸化膜５１をエッチングする。こうしてマスクが形成される。このシリコン酸化膜５１を用いて、その後、ＲＩＥにより低抵抗層４３についてＳｉＣエッチングを行い、低抵抗層４３を利用して前述したエミッタ領域１２を形成する。ＳｉＣエッチングのＲＩＥにはＳＦ６ガスなどが用いられる。その結果得られた構造を図６Ａの（ｂ）に示す。 In the next emitter etching process (step S14), in the structure shown in FIG. 6A (a), a silicon oxide film 51 is deposited on the upper surface by CVD, photolithography is performed, and then silicon oxide is formed by RIE. The film 51 is etched. Thus, a mask is formed. Then, using this silicon oxide film 51, SiC etching is performed on the low resistance layer 43 by RIE, and the emitter region 12 is formed using the low resistance layer 43. SF 6 gas or the like is used for RIE of SiC etching. The resulting structure is shown in FIG. 6A (b).
　再結合抑制領域を形成するプロセス（ステップＳ１５）では、さらに図６Ａの（ｃ）に示されるように、図６Ａ（ｂ）に示したマスク５１をそのまま利用して再結合抑制領域１６を形成する。再結合抑制領域１６の形成は、不純物（イオン種）として窒素のイオン注入を行うことにより行われる。エミッタエッチングプロセス（ステップＳ１５）によりエッチングされたすべての領域にイオン注入がなされる。再結合抑制領域の特性を抵抗率の高い「ｐ－」または［ｎ－］にするために、イオン注入量はベース領域４２の不純物濃度と同程度かその前後の値に設定される。例えばベース領域４２の不純物濃度が４×１０１７ｃｍ－３であればイオン注入量は３～５×１０１７ｃｍ－３程度が望ましい。また再結合抑制領域１６は表面の極近傍の再結合準位を含めば良いので、その深さは０．１～０．２μｍ程度で良い。そのため注入エネルギーを１００ｋｅＶ程度に低く抑えることができ、イオン注入プロセスでの結晶欠陥の生成を抑制することができる。 In the process of forming the recombination suppression region (step S15), as shown in FIG. 6A (c), the recombination suppression region 16 is formed using the mask 51 shown in FIG. 6A (b) as it is. . The recombination suppression region 16 is formed by performing ion implantation of nitrogen as an impurity (ion species). Ions are implanted into all regions etched by the emitter etching process (step S15). In order to set the characteristics of the recombination suppression region to “p − ” or [n − ] having a high resistivity, the ion implantation amount is set to a value approximately equal to or around the impurity concentration of the base region 42. For example, if the impurity concentration of the base region 42 is 4 × 10 17 cm −3 , the ion implantation amount is desirably about 3 to 5 × 10 17 cm −3 . Further, since the recombination suppression region 16 only needs to include a recombination level in the vicinity of the surface, its depth may be about 0.1 to 0.2 μm. Therefore, the implantation energy can be suppressed to as low as about 100 keV, and the generation of crystal defects in the ion implantation process can be suppressed.
　ベースコンタクト領域形成プロセス（ステップＳ１６）では、最初に、図６Ａ（ｄ）に示すように、ベースコンタクト領域１３を形成するための表面部分が露出するようにマスク５２が形成される。マスク５２は、ＣＶＤ法によりシリコン酸化膜を堆積し、フォトリソグラフィーを行い、その後にＲＩＥによりシリコン酸化膜をエッチングすることにより形成される。その後、イオン注入を行ってベースコンタクト領域１３を形成する。注入されるイオンはアルミニウム（Ａｌ）であり、注入の深さは例えば０．２μｍである。イオン注入量は１×１０１８～１０２０ｃｍ－３であり、イオン注入に必要なエネルギはほぼ２００ＫｅＶである。 In the base contact region forming process (step S16), first, as shown in FIG. 6A (d), a mask 52 is formed so that the surface portion for forming the base contact region 13 is exposed. The mask 52 is formed by depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, ion implantation is performed to form the base contact region 13. The implanted ions are aluminum (Al), and the depth of implantation is, for example, 0.2 μm. The ion implantation amount is 1 × 10 18 to 10 20 cm −3 , and the energy required for ion implantation is approximately 200 KeV.
　上記のステップＳ１５，Ｓ１６によってベースコンタクト領域１３とエミッタ領域１２の間におけるベース領域１５の表面には再結合抑制領域１６が形成される。再結合抑制領域１６を設けることはエミッタ領域１２から到来する電子を再結合抑制領域１６のＳｉＣ表面から遠ざけることが目的である。 The recombination suppression region 16 is formed on the surface of the base region 15 between the base contact region 13 and the emitter region 12 by the above steps S15 and S16. The purpose of providing the recombination suppression region 16 is to keep electrons coming from the emitter region 12 away from the SiC surface of the recombination suppression region 16.
　次に、イオン注入層を活性化するプロセス（ステップＳ１７）では、イオン注入後に、注入イオンを半導体中で電気的に活性化すると共に、イオン注入で発生した結晶欠陥を消すための熱処理を行う（図６Ｂ（ｅ））。この活性化の熱処理では、ベースコンタクト領域１３の注入イオンと再結合抑制領域１６の注入イオンの両方の活性化を同時に行っている。高周波熱処理炉などを用い、１７００～１８００℃程度の高温下で約１０分程度の熱処理を行う。雰囲気ガスには例えばアルゴンガス（Ａｒ）が用いられる。 Next, in the process of activating the ion implantation layer (step S17), after the ion implantation, the implanted ions are electrically activated in the semiconductor, and a heat treatment is performed to eliminate crystal defects generated by the ion implantation ( FIG. 6B (e)). In this activation heat treatment, both the implanted ions in the base contact region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time. Using a high-frequency heat treatment furnace or the like, heat treatment is performed at a high temperature of about 1700 to 1800 ° C. for about 10 minutes. For example, argon gas (Ar) is used as the atmospheric gas.
　表面保護膜を形成するプロセス（ステップＳ１８）では、図６Ｂ（ｆ）で示すように、初めに、イオン注入工程と活性化工程で生じた表面層を取り除くために、熱酸化後に酸化膜を取り除く犠牲酸化を行う。酸化条件は、例えばドライ酸素中で１１００℃、２０時間などである。酸化膜の除去にはフッ化水素酸を用いる。犠牲酸化後に再び熱酸化を行い酸化膜５３を形成する。熱酸化膜形成では、例えば、温度が１１００℃、時間が５時間、雰囲気はウェットである。その後に、ＳｉＣ酸化膜界面の不純物準位を低減するための熱処理（ＰＯＡ：Post Oxidation Anneal)を行う。ＰＯＡは、水素や酸化窒素（ＮＯ、Ｎ２Ｏ）またはアルゴン雰囲気中で、８００～１３００℃程度の高温下で、１０～３０分程度、行う。ＰＯＡ後、ＣＶＤ酸化膜やＣＶＤ窒化膜を形成する。 In the process of forming the surface protective film (step S18), as shown in FIG. 6B (f), first, in order to remove the surface layer generated in the ion implantation process and the activation process, the oxide film is removed after the thermal oxidation. Perform sacrificial oxidation. The oxidation condition is, for example, 1100 ° C. for 20 hours in dry oxygen. Hydrofluoric acid is used to remove the oxide film. After the sacrificial oxidation, thermal oxidation is performed again to form an oxide film 53. In the formation of the thermal oxide film, for example, the temperature is 1100 ° C., the time is 5 hours, and the atmosphere is wet. Thereafter, heat treatment (POA: Post Oxidation Anneal) is performed to reduce the impurity level at the interface of the SiC oxide film. POA is performed in a hydrogen, nitrogen oxide (NO, N 2 O) or argon atmosphere at a high temperature of about 800 to 1300 ° C. for about 10 to 30 minutes. After POA, a CVD oxide film or a CVD nitride film is formed.
　電極を形成するプロセス（ステップＳ１９）では、エミッタ領域１２（低抵抗層４３）、ベースコンタクト領域１３、コレクタ領域１１（基板４０）の各々の表面にエミッタ電極１９、ベース電極２０、コレクタ電極１８を形成する（図６Ｂ（ｇ））。残った上記の酸化膜５３が前述した表面保護膜１７になる。エミッタ電極１９、コレクタ電極１８にはニッケルやチタンを用い、ベース電極２０にはチタンやアルミニウムなどを用いる。各電極１８，１９，２０は、蒸着やスパッタリングなどで形成する。電極パターンの形成には、ドライエッチング、ウェットエッチング、リフトオフ法などが利用される。 In the process of forming electrodes (step S19), the emitter electrode 19, the base electrode 20, and the collector electrode 18 are formed on the surfaces of the emitter region 12 (low resistance layer 43), the base contact region 13, and the collector region 11 (substrate 40), respectively. It forms (FIG. 6B (g)). The remaining oxide film 53 becomes the surface protective film 17 described above. The emitter electrode 19 and the collector electrode 18 are made of nickel or titanium, and the base electrode 20 is made of titanium or aluminum. Each electrode 18, 19, 20 is formed by vapor deposition or sputtering. For the formation of the electrode pattern, dry etching, wet etching, lift-off method or the like is used.
　電極１８～２０を形成した後には、金属部分と半導体部分との間の接触抵抗を低減するために熱処理を行う。当該熱処理の条件は、温度条件が８００～１０００℃、時間条件が１０～３０分程度である。 After the electrodes 18 to 20 are formed, heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion. The heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.
　最後に上層電極形成プロセス（ステップＳ２０）が実行される。この上層電極形成工程（ステップＳ２０）では、分離されている複数のエミッタ電極１９を１つの電極に取り出すための上層電極５４を形成する（図６Ｂ（ｈ））。ＣＶＤ法によりシリコン酸化膜などを層間膜５５として形成した後、フォトリソグラフィーとエッチングによりエミッタ電極１９の部分のシリコン酸化膜などを取り除く。こうしてエミッタ電極１９を露出させた後に、上層電極５４を堆積させる。上層電極５４の材料には例えばアルミニウム（Ａｌ）を用いる。 Finally, the upper layer electrode formation process (step S20) is executed. In this upper layer electrode formation step (step S20), an upper layer electrode 54 for taking out a plurality of separated emitter electrodes 19 as one electrode is formed (FIG. 6B (h)). After the silicon oxide film or the like is formed as the interlayer film 55 by the CVD method, the silicon oxide film or the like in the emitter electrode 19 is removed by photolithography and etching. After exposing the emitter electrode 19 in this way, the upper layer electrode 54 is deposited. For example, aluminum (Al) is used as the material of the upper electrode 54.
　このようにして、図１と図２で示したＢＪＴ１０が作製される。当該ＢＪＴ１０は、ノーマリオフ特性を有する高性能の半導体装置である。 In this way, the BJT 10 shown in FIGS. 1 and 2 is manufactured. The BJT 10 is a high-performance semiconductor device having normally-off characteristics.
　上記第１実施例において、コレクタ領域、エミッタ領域、高抵抗層、ベース領域、ベースコンタクト領域、再結合抑制領域等の第１および第２の導電型の組合せをすべて逆にして構成することもできる。この点については、以下に説明する他の実施例においても同様である。 In the first embodiment, the combinations of the first and second conductivity types such as the collector region, the emitter region, the high resistance layer, the base region, the base contact region, and the recombination suppression region can be reversed. . This also applies to the other embodiments described below.
　＜第２実施例＞
　図７と図８を参照して本発明によるバイポーラ型半導体装置の第２実施例を説明する。第２実施例のバイポーラ型半導体装置も同様にＢＪＴである。図７において、図１で説明した要素と実質的に同一の要素には同一の符号を付している。 <Second embodiment>
A second embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS. The bipolar semiconductor device of the second embodiment is also BJT. In FIG. 7, elements that are substantially the same as those described in FIG. 1 are given the same reference numerals.
　図３に示すように、従来構造のＢＪＴ１０Ａではエミッタ領域１２をベース領域１５の表面が露出するまでエッチングする。このようにエッチングプロセスの精度の限界からベース領域１５の一部をエッチングせざるを得ないため、ベース層の厚さが薄くなり、その結果ベースの抵抗値が大きくなる。またエッチング深さのウエハ内またはウエハ間のばらつきにより、ベース抵抗値もウエハ内またはウエハ間でばらつくことになる。さらに、ＢＪＴの電流増幅率を向上させるためにはベース層を薄くすることが望ましいが、ベース層を薄くするとエッチングプロセスに起因するベース抵抗の増大や値のばらつきがより顕著になる。 As shown in FIG. 3, in the conventional BJT 10A, the emitter region 12 is etched until the surface of the base region 15 is exposed. Thus, since a part of the base region 15 must be etched due to the limit of the accuracy of the etching process, the thickness of the base layer is reduced, and as a result, the resistance value of the base is increased. In addition, the base resistance value varies between wafers or between wafers due to variations in etching depth within a wafer or between wafers. Further, in order to improve the current amplification factor of the BJT, it is desirable to make the base layer thinner. However, if the base layer is made thinner, the increase in base resistance and the variation in value due to the etching process become more remarkable.
　そこで、第２実施例によるＢＪＴ１００では、層状に形成されたベース領域１５において、エッチングにより露出したベース表面の領域に対応する領域に、ベース領域と同等またはそれ以下の抵抗率を有するｐ型半導体（ｐ＋またはｐ－）からなる低抵抗埋め込み領域６１を設けるようにしている。本実施例では、第１実施例のように表面の再結合抑制領域１６は形成されない。その他の構造は第１実施例の構造と同じである。 Therefore, in the BJT 100 according to the second embodiment, a p-type semiconductor having a resistivity equal to or lower than that of the base region in a region corresponding to the region of the base surface exposed by etching in the base region 15 formed in a layer shape ( A low resistance buried region 61 made of p + or p − ) is provided. In this embodiment, the surface recombination suppression region 16 is not formed as in the first embodiment. Other structures are the same as those of the first embodiment.
　上記の構造によれば、ベースコンタクト領域１３からベース領域１５に流れ込む正孔電流は、図３で示した従来例では表面付近に流れていたのに対して、図８に示すように抵抗値のより低い低抵抗埋め込み領域６１に流れることになる。そのため、ベース領域１５の表面付近での再結合が低減され、電流増幅率が向上する。 According to the above structure, the hole current flowing from the base contact region 13 to the base region 15 flows near the surface in the conventional example shown in FIG. 3, whereas the resistance value as shown in FIG. It flows to the lower low resistance buried region 61. Therefore, recombination near the surface of base region 15 is reduced, and the current amplification factor is improved.
　低抵抗埋め込み領域６１はベース領域１５に対してより低い抵抗値であるため、ベース領域１５の抵抗は低抵抗埋め込み領域６１の抵抗値によって決まることになる。これにより上記のエッチングによって生じたベース領域１５の高抵抗化とばらつきを低減することができる。 Since the low-resistance buried region 61 has a lower resistance value than the base region 15, the resistance of the base region 15 is determined by the resistance value of the low-resistance buried region 61. As a result, it is possible to increase the resistance and variation of the base region 15 caused by the etching.
　ｐ型のベース領域１５の不純物濃度は前述した通り４×１０１７～２×１０１８ｃｍ－３であるのに対して、低抵抗埋め込み領域６１の不純物濃度はベース領域１５と同程度以上の濃度とする。例えば、ｐ型のベース領域１５の不純物濃度が例えば４×１０１７ｃｍ－３であった場合には、低抵抗埋め込み領域６１の不純物濃度を２×１０１８ｃｍ－３とし、かつその厚みをベース領域６１の厚みと同じにすると、低抵抗埋め込み領域６１の抵抗率はベース領域１５の抵抗率に対して１／３に低減できる。 whereas the impurity concentration of the p-type base region 15 are as 4 × 10 17 ~ 2 × 10 18 cm -3 as described above, the concentration of more than the same level as the base region 15 the impurity concentration of the low-resistance buried region 61 And For example, when the impurity concentration of the p-type base region 15 is, for example, 4 × 10 17 cm −3 , the impurity concentration of the low-resistance buried region 61 is set to 2 × 10 18 cm −3 and the thickness thereof is set as the base. If the thickness of the region 61 is the same, the resistivity of the low-resistance buried region 61 can be reduced to 1/3 of the resistivity of the base region 15.
　第２実施例のＢＪＴ１００の製造方法について、特に上記の低抵抗埋め込み領域６１は、前述した第１実施例のＢＪＴ１０の製造方法において、多段のイオン注入法を適用することによって形成することができる。 Regarding the manufacturing method of the BJT 100 of the second embodiment, the low resistance buried region 61 can be formed by applying a multi-stage ion implantation method in the manufacturing method of the BJT 10 of the first embodiment described above.
　＜第３実施例＞
　図９と図１０を参照して本発明によるバイポーラ型半導体装置の第３実施例を説明する。第３実施例のバイポーラ型半導体装置もＢＪＴである。図９において、図１で説明した要素と実質的に同一の要素には同一の符号を付している。 <Third embodiment>
A third embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS. The bipolar semiconductor device of the third embodiment is also a BJT. 9, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals.
　図３で説明したように、従来構造のＢＪＴ１０Ａでは、ベース領域１５を流れる正孔とコレクタ領域１１を流れる電子とが、ベース・コレクタ界面付近で再結合するという特性を有している。 As shown in FIG. 3, the BJT 10A having the conventional structure has a characteristic that the holes flowing through the base region 15 and the electrons flowing through the collector region 11 are recombined near the base-collector interface.
　そこで、第３実施例のＢＪＴ２００では、層状に形成されたベース領域１５の下側（高抵抗層１４側）において、前述したエッチングにより露出したベース表面の領域に対応する領域で、当該ベース領域１５に接した状態でベース領域１５よりも高抵抗のｐ型半導体（ｐ－）からなる高抵抗埋め込み領域または高抵抗層１４よりも高抵抗のｎ型半導体（ｎ－）からなる高抵抗埋め込み領域６３を設ける。本実施例では、第１実施例のようにベース表面の再結合抑制領域１６は形成されない。その他の構造は第１実施例の構造と同じである。 Therefore, in the BJT 200 of the third embodiment, the base region 15 is a region corresponding to the region of the base surface exposed by the etching described above on the lower side (on the high resistance layer 14 side) of the base region 15 formed in layers. A high resistance buried region made of a p-type semiconductor (p − ) having a higher resistance than the base region 15 or a high resistance buried region 63 made of an n-type semiconductor (n − ) having a higher resistance than the high resistance layer 14 in contact with the base region 15. Is provided. In this embodiment, the recombination suppression region 16 on the base surface is not formed as in the first embodiment. Other structures are the same as those of the first embodiment.
　第３実施例のＢＪＴ２００の構造では、高抵抗埋め込み領域６３を設けることにより、ｐ－層である場合には、その存在で高抵抗埋め込み領域６３と高抵抗層１４の間に部分的にポテンシャル（電位差）が形成され、当該高抵抗層１４の電子がベース領域１５から遠ざけられる。また高抵抗埋め込み領域６３内の正孔の濃度はベース領域１５の正孔濃度よりも低い。このため、従来構造のＢＪＴ１０Ａにおけるベース領域・高抵抗層付近の電子・正孔の濃度と比較して、第３実施例での高抵抗埋め込み領域・高抵抗層付近の電子・正孔濃度が低いために再結合を低減することができ、これにより電流増幅率を向上することができる。またｎ－層である場合にも、ほぼ同様の原理で再結合を抑制でき電流増幅率を向上することができる。 In the structure of the BJT 200 of the third embodiment, by providing the high-resistance buried region 63, in the case of the p − layer, a potential (partially between the high-resistance buried region 63 and the high-resistance layer 14 exists in the presence thereof. Potential difference) is formed, and the electrons of the high resistance layer 14 are moved away from the base region 15. The hole concentration in the high resistance buried region 63 is lower than the hole concentration in the base region 15. For this reason, the electron / hole concentration in the high resistance buried region / high resistance layer in the third embodiment is lower than that in the base region / high resistance layer vicinity in the BJT 10A having the conventional structure. Therefore, recombination can be reduced, thereby improving the current amplification factor. Even in the case of the n − layer, recombination can be suppressed by substantially the same principle, and the current amplification factor can be improved.
　ｐ型のベース領域１５の不純物濃度は前述した通り４×１０１７～２×１０１８ｃｍ－３であるのに対して、高抵抗埋め込み領域６３の不純物濃度はベース領域１５と同程度以下の濃度とする。例えば、ｐ型のベース領域１５の不純物濃度が例えば４×１０１７ｃｍ－３であった場合には、高抵抗埋め込み領域６３の不純物濃度を１×１０１７ｃｍ－３以下とする。 As described above, the impurity concentration of the p-type base region 15 is 4 × 10 17 to 2 × 10 18 cm −3 , whereas the impurity concentration of the high-resistance buried region 63 is less than or equal to that of the base region 15. And For example, when the impurity concentration of the p-type base region 15 is, for example, 4 × 10 17 cm −3 , the impurity concentration of the high-resistance buried region 63 is set to 1 × 10 17 cm −3 or less.
　＜第４実施例＞
　図１１を参照して本発明によるバイポーラ型半導体装置の第４実施例を説明する。図１１において図７や図９で説明した要素と実質的に同一の要素には同一の符号を付している。 <Fourth embodiment>
A bipolar semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. 11, elements that are substantially the same as those described in FIGS. 7 and 9 are denoted by the same reference numerals.
　第４実施例のＢＪＴ３００は、第２および第３実施例の特徴的構造を組み合わせて構成される。第４実施例では、低抵抗埋め込み領域６１の下面に接するように高抵抗埋め込み領域６３が形成されている。その他の構成については、第２または第３実施例の構成と同じである。本実施例のＢＪＴ３００によっても、前述した同様な効果が発揮される。 The BJT 300 of the fourth embodiment is configured by combining the characteristic structures of the second and third embodiments. In the fourth embodiment, the high resistance buried region 63 is formed so as to be in contact with the lower surface of the low resistance buried region 61. Other configurations are the same as those of the second or third embodiment. The same effect as described above is also exhibited by the BJT 300 of the present embodiment.
　＜第５実施例＞
　図１２を参照して本発明によるバイポーラ型半導体装置の第５実施例を説明する。図１２において図１、図７、図９で説明した要素と実質的に同一の要素には同一の符号を付している。 <Fifth embodiment>
A fifth embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIG. 12, elements that are substantially the same as those described in FIGS. 1, 7, and 9 are denoted by the same reference numerals.
　第５実施例のＢＪＴ４００は、第１、第２および第３実施例の特徴的構造を組み合わせて構成される。第５実施例では、再結合抑制領域１６、低抵抗埋め込み領域６１、当該低抵抗埋め込み領域６１の下面に接するように形成された高抵抗埋め込み領域６３が設けられている。その他の構成については、第１、第２、または第３実施例の構成と同じである。本実施例のＢＪＴ４００によっても、前述した同様な効果が発揮される。 The BJT 400 of the fifth embodiment is configured by combining the characteristic structures of the first, second and third embodiments. In the fifth embodiment, a recombination suppression region 16, a low-resistance buried region 61, and a high-resistance buried region 63 formed so as to be in contact with the lower surface of the low-resistance buried region 61 are provided. Other configurations are the same as those of the first, second, or third embodiment. The same effect as described above is also exhibited by the BJT 400 of the present embodiment.
　本実施例においては、製造方法の工程の説明中のｐとｎの極性を逆にした逆極性タイプのものでも良い。さらに本実施例では、ＳｉＣの例について説明したが、本発明は表面再結合が問題となる他の半導体にも適用できる。 In this embodiment, a reverse polarity type in which the polarities of p and n in the description of the process of the manufacturing method are reversed may be used. Furthermore, in this embodiment, an example of SiC has been described, but the present invention can also be applied to other semiconductors in which surface recombination is a problem.
　以上の各実施例で説明された構成、形状、大きさおよび配置関係については本発明が理解・実施できる程度に概略的に示したものにすぎず、また数値および各構成の組成（材質）等については例示にすぎない。従って本発明は、説明された実施例に限定されるものではなく、請求の範囲に示される技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。 The configurations, shapes, sizes, and arrangement relationships described in each of the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented, and numerical values and compositions (materials) of the respective components. Is merely an example. Therefore, the present invention is not limited to the described embodiments, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.
　本発明は、４層構造を有する従来の一般的なバイポーラ型炭化珪素半導体装置で、主電流の電子が制御電流の正孔と再結合することを抑制して電流増幅率を向上すること、およびベース層を薄くしてもベース抵抗値の増大やばらつきを改善することに利用され、さらにかかる特性を有するバイポーラ型炭化珪素半導体装置を作製する方法に利用する。 The present invention relates to a conventional general bipolar silicon carbide semiconductor device having a four-layer structure, which suppresses recombination of electrons of a main current with holes of a control current and improves a current amplification factor, and Even if the base layer is thinned, it is used for improving an increase or variation in the base resistance value, and further used for a method of manufacturing a bipolar silicon carbide semiconductor device having such characteristics.
　１０　バイポーラ型半導体装置（ＢＪＴ）
　１１　コレクタ領域
　１２　エミッタ領域
　１３　ベースコンタクト領域
　１４　高抵抗層
　１５　ベース領域
　１６　再結合抑制領域
　１７　表面保護膜
　１８　コレクタ電極
　１９　エミッタ電極
　２０　ベース電極
　２１　上層電極
　４０　基板
　４１　高抵抗層
　４２　ベース領域
　４３　低抵抗層
　６１　低抵抗埋め込み領域
　６３　高抵抗埋め込み領域
　１００　ＢＪＴ
　２００　ＢＪＴ
　３００　ＢＪＴ
　４００　ＢＪＴ 10 Bipolar semiconductor devices (BJT)
DESCRIPTION OF SYMBOLS 11 Collector area | region 12 Emitter area | region 13 Base contact area | region 14 High resistance layer 15 Base area | region 16 Recombination suppression area | region 17 Surface protective film 18 Collector electrode 19 Emitter electrode 20 Base electrode 21 Upper layer electrode 40 Substrate 41 High resistance layer 42 Base area 43 Low resistance Layer 61 Low resistance buried region 63 High resistance buried region 100 BJT
200 BJT
300 BJT
400 BJT

Claims (12)

  1. 　炭化珪素半導体結晶で作られた基板であるコレクタ領域と、
    　前記コレクタ領域の上に形成された高抵抗層と、
    　前記高抵抗層の上に形成されたベース領域と、
    　低抵抗層からなり、前記ベース領域と接合されるエミッタ領域と、
    　前記エミッタ領域の周囲に形成され、前記ベース領域に接合する低抵抗のベースコンタクト領域と、
    　前記ベースコンタクト領域と前記エミッタ領域との間の表面付近に形成され、前記ベース領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域、または前記エミッタ領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域と、
    　を備えているバイポーラ型炭化珪素半導体装置。     A collector region which is a substrate made of a silicon carbide semiconductor crystal;
    A high resistance layer formed on the collector region;
    A base region formed on the high resistance layer;
    An emitter region composed of a low resistance layer and joined to the base region;
    A low-resistance base contact region formed around the emitter region and joined to the base region;
    A recombination suppression region formed near the surface between the base contact region and the emitter region, having the same conductivity type as the base region and having a higher resistivity than the base region, or having the same conductivity type as the emitter region; Recombination suppression region higher than its resistivity,
    A bipolar silicon carbide semiconductor device comprising:
  2. 　前記コレクタ領域は第１の導電型の低抵抗層であり、前記エミッタ領域は第１の導電型の低抵抗層であり、前記高抵抗層は第１の導電型であり、前記ベース領域は第２の導電型である請求項１に記載のバイポーラ型炭化珪素半導体装置。 The collector region is a first conductivity type low resistance layer, the emitter region is a first conductivity type low resistance layer, the high resistance layer is a first conductivity type, and the base region is a first resistance type. 2. The bipolar silicon carbide semiconductor device according to claim 1, wherein the bipolar silicon carbide semiconductor device is of a conductivity type of 2.
  3. 　炭化珪素半導体結晶で作られた基板であるコレクタ領域と、
    　前記コレクタ領域の上に形成された高抵抗層と、
    　前記高抵抗層の上に形成されたベース領域と、
    　低抵抗層からなり、前記ベース領域と接合されるエミッタ領域と、
    　前記エミッタ領域の周囲に形成され、前記ベース領域に接合する低抵抗のベースコンタクト領域と、
    　前記ベース領域に形成され、前記ベースコンタクト領域に接すると共に、前記ベース領域と同じ導電型でありかつその抵抗率と同等かまたは当該抵抗率よりも低い埋め込み領域と、
    　を備えているバイポーラ型炭化珪素半導体装置。     A collector region which is a substrate made of a silicon carbide semiconductor crystal;
    A high resistance layer formed on the collector region;
    A base region formed on the high resistance layer;
    An emitter region composed of a low resistance layer and joined to the base region;
    A low-resistance base contact region formed around the emitter region and joined to the base region;
    A buried region formed in the base region, in contact with the base contact region, having the same conductivity type as the base region and having a resistivity equal to or lower than the resistivity;
    A bipolar silicon carbide semiconductor device comprising:
  4. 　前記コレクタ領域は第１の導電型の低抵抗層であり、前記エミッタ領域は第１の導電型の低抵抗層であり、前記高抵抗層は第１の導電型であり、前記ベース領域は第２の導電型である請求項３に記載のバイポーラ型炭化珪素半導体装置。 The collector region is a first conductivity type low resistance layer, the emitter region is a first conductivity type low resistance layer, the high resistance layer is a first conductivity type, and the base region is a first resistance type. The bipolar silicon carbide semiconductor device according to claim 3, wherein the bipolar silicon carbide semiconductor device is of conductivity type 2.
  5. 　炭化珪素半導体結晶で作られた基板であるコレクタ領域と、
    　前記コレクタ領域の上に形成された高抵抗層と、
    　前記高抵抗層の上に形成されたベース領域と、
    　低抵抗層からなり、前記ベース領域と接合されるエミッタ領域と、
    　前記エミッタ領域の周囲に形成され、前記ベース領域に接合する低抵抗のベースコンタクト領域と、
    　前記高抵抗層に形成され、前記ベース領域に接すると共に、前記ベース領域と同じ導電型でありかつその抵抗率よりも高い埋め込み領域、または前記高抵抗領域と同じ導電型でありかつその抵抗率よりも高い埋め込み領域と、
    　を備えているバイポーラ型炭化珪素半導体装置。     A collector region which is a substrate made of a silicon carbide semiconductor crystal;
    A high resistance layer formed on the collector region;
    A base region formed on the high resistance layer;
    An emitter region composed of a low resistance layer and joined to the base region;
    A low-resistance base contact region formed around the emitter region and joined to the base region;
    An embedded region formed on the high resistance layer and in contact with the base region and having the same conductivity type as the base region and having a higher resistivity than the base region, or having the same conductivity type as the high resistance region and the resistivity With a higher buried area,
    A bipolar silicon carbide semiconductor device comprising:
  6. 　前記コレクタ領域は第１の導電型の低抵抗層であり、前記エミッタ領域は第１の導電型の低抵抗層であり、前記高抵抗層は第１の導電型であり、前記ベース領域は第２の導電型である請求項５に記載のバイポーラ型炭化珪素半導体装置。 The collector region is a first conductivity type low resistance layer, the emitter region is a first conductivity type low resistance layer, the high resistance layer is a first conductivity type, and the base region is a first resistance type. The bipolar silicon carbide semiconductor device according to claim 5, wherein the bipolar silicon carbide semiconductor device is of conductivity type 2.
  7. 　炭化珪素の半導体結晶で作られかつコレクタ領域となる基板の上に高抵抗層を形成する第１の工程と、
    　前記高抵抗層の上にベース領域を形成する第２の工程と、
    　前記ベース領域の上に低抵抗層を形成するための第３の工程と、
    　前記低抵抗層を部分的にエッチングしてエミッタ領域を形成する第４の工程と、
    　エッチングにより露出した前記ベース領域の表面付近に、前記ベース領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域、または前記エミッタ領域と同じ導電型でありかつその抵抗率よりも高い再結合抑制領域を形成する第５の工程と、
    　前記ベース領域に接合するベースコンタクト領域を形成する第６の工程と、
    　を含むバイポーラ型炭化珪素半導体装置の製造方法。     Forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a collector region;
    A second step of forming a base region on the high resistance layer;
    A third step for forming a low resistance layer on the base region;
    A fourth step of partially etching the low resistance layer to form an emitter region;
    Near the surface of the base region exposed by etching, a recombination suppression region having the same conductivity type as that of the base region and higher in resistivity, or having the same conductivity type as that of the emitter region and higher than its resistivity. A fifth step of forming a recombination suppression region;
    A sixth step of forming a base contact region joined to the base region;
    Of manufacturing a bipolar silicon carbide semiconductor device comprising:
  8. 　前記コレクタ領域、前記エミッタ領域、および前記ベースコンタクト領域のそれぞれに、コレクタ電極、エミッタ電極、ベース電極を形成する工程と、
    　前記エミッタ電極と前記ベース電極の上側に上層電極を形成する工程と、
    　をさらに含む請求項７に記載のバイポーラ型炭化珪素半導体装置の製造方法。     Forming a collector electrode, an emitter electrode, and a base electrode in each of the collector region, the emitter region, and the base contact region;
    Forming an upper layer electrode above the emitter electrode and the base electrode;
    The method for manufacturing a bipolar silicon carbide semiconductor device according to claim 7, further comprising:
  9. 　炭化珪素の半導体結晶で作られかつコレクタ領域となる基板の上に高抵抗層を形成する第１の工程と、
    　前記高抵抗層の上にベース領域を形成する第２の工程と、
    　前記ベース領域の上に低抵抗層を形成するための第３の工程と、
    　前記低抵抗層を部分的にエッチングしてエミッタ領域を形成する第４の工程と、
    　前記ベース領域に、前記ベースコンタクト領域に接すると共に、前記ベース領域と同じ導電型でありかつその抵抗率と同等かまたは当該抵抗率よりも低い埋め込み領域を形成する第５の工程と、
    　前記ベース領域に接合するベースコンタクト領域を形成する第６の工程と、
    　を含むバイポーラ型炭化珪素半導体装置の製造方法。     Forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a collector region;
    A second step of forming a base region on the high resistance layer;
    A third step for forming a low resistance layer on the base region;
    A fourth step of partially etching the low resistance layer to form an emitter region;
    A fifth step of forming, in the base region, a buried region that is in contact with the base contact region and has the same conductivity type as the base region and has a resistivity equal to or lower than the resistivity;
    A sixth step of forming a base contact region joined to the base region;
    Of manufacturing a bipolar silicon carbide semiconductor device comprising:
  10. 　前記コレクタ領域、前記エミッタ領域、および前記ベースコンタクト領域のそれぞれに、コレクタ電極、エミッタ電極、ベース電極を形成する工程と、
    　前記エミッタ電極と前記ベース電極の上側に上層電極を形成する工程と、
    　をさらに含む請求項９に記載のバイポーラ型炭化珪素半導体装置の製造方法。     Forming a collector electrode, an emitter electrode, and a base electrode in each of the collector region, the emitter region, and the base contact region;
    Forming an upper layer electrode above the emitter electrode and the base electrode;
    The method for manufacturing a bipolar silicon carbide semiconductor device according to claim 9, further comprising:
  11. 　炭化珪素の半導体結晶で作られかつコレクタ領域となる基板の上に高抵抗層を形成する第１の工程と、
    　前記高抵抗層の上にベース領域を形成する第２の工程と、
    　前記ベース領域の上に低抵抗層を形成するための第３の工程と、
    　前記低抵抗層を部分的にエッチングしてエミッタ領域を形成する第４の工程と、
    　前記高抵抗層に、前記ベース領域に接すると共に、前記ベース領域と同じ導電型でありかつその抵抗率よりも高い埋め込み領域、または前記期エミッタ領域と同じ導電型でありかつその抵抗率よりも高い埋め込み領域を形成する第５の工程と、
    　前記ベース領域に接合するベースコンタクト領域を形成する第６の工程と、
    　を含むことを特徴とするバイポーラ型炭化珪素半導体装置の製造方法。     A first step of forming a high resistance layer on a substrate made of a semiconductor crystal of silicon carbide and serving as a collector region;
    A second step of forming a base region on the high resistance layer;
    A third step for forming a low resistance layer on the base region;
    A fourth step of partially etching the low resistance layer to form an emitter region;
    The high resistance layer is in contact with the base region and has the same conductivity type as the base region and has a higher resistivity than the buried region, or the same conductivity type as the initial emitter region and higher than the resistivity A fifth step of forming a buried region;
    A sixth step of forming a base contact region joined to the base region;
    A method for manufacturing a bipolar silicon carbide semiconductor device, comprising:
  12. 　前記コレクタ領域、前記エミッタ領域、および前記ベースコンタクト領域のそれぞれに、コレクタ電極、エミッタ電極、ベース電極を形成する工程と、
    　前記エミッタ電極と前記ベース電極の上側に上層電極を形成する工程と、
    　をさらに含む請求項１１に記載のバイポーラ型炭化珪素半導体装置の製造方法。     Forming a collector electrode, an emitter electrode, and a base electrode in each of the collector region, the emitter region, and the base contact region;
    Forming an upper layer electrode above the emitter electrode and the base electrode;
    The method for manufacturing a bipolar silicon carbide semiconductor device according to claim 11, further comprising:
PCT/JP2009/064770 2008-08-26 2009-08-25 Bipolar silicon carbide semiconductor device and method for manufacturing same WO2010024240A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010526712A JP5469068B2 (en) 2008-08-26 2009-08-25 Bipolar silicon carbide semiconductor device and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008217386 2008-08-26
JP2008-217386 2008-08-26

Publications (1)

Publication Number Publication Date
WO2010024240A1 true WO2010024240A1 (en) 2010-03-04

Family

ID=41721408

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/064770 WO2010024240A1 (en) 2008-08-26 2009-08-25 Bipolar silicon carbide semiconductor device and method for manufacturing same

Country Status (2)

Country Link
JP (1) JP5469068B2 (en)
WO (1) WO2010024240A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012105899A1 (en) * 2011-01-31 2012-08-09 Fairchild Semiconductor Corporation Sic bipolar junction transistor with overgrown emitter
JP2013041985A (en) * 2011-08-16 2013-02-28 Shindengen Electric Mfg Co Ltd Silicon carbide semiconductor device
JP2015018859A (en) * 2013-07-09 2015-01-29 国立大学法人京都大学 Semiconductor device, method of manufacturing semiconductor device, and thermal treatment apparatus
US9478629B2 (en) 2010-07-14 2016-10-25 Fairchild Semiconductor Corporation Conductivity modulation in a silicon carbide bipolar junction transistor

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS645063A (en) * 1987-06-29 1989-01-10 Toshiba Corp Hetero-junction bipolar transistor
JPH06244195A (en) * 1993-02-17 1994-09-02 Sharp Corp Semiconductor device
JP2002359378A (en) * 2001-03-28 2002-12-13 Toshiba Corp Semiconductor device and its manufacturing method
JP2006351621A (en) * 2005-06-13 2006-12-28 Honda Motor Co Ltd Bipolar semiconductor device and its manufacturing method
JP2007173841A (en) * 2005-12-22 2007-07-05 Cree Inc Silicon carbide bipolar junction transistor having silicon carbide passivation layer on base region and method of fabricating thereof
JP2007287782A (en) * 2006-04-13 2007-11-01 Hitachi Ltd Mesa bipolar transistor
JP2009054931A (en) * 2007-08-29 2009-03-12 Hitachi Ltd Bipolar element and its manufacturing method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS645063A (en) * 1987-06-29 1989-01-10 Toshiba Corp Hetero-junction bipolar transistor
JPH06244195A (en) * 1993-02-17 1994-09-02 Sharp Corp Semiconductor device
JP2002359378A (en) * 2001-03-28 2002-12-13 Toshiba Corp Semiconductor device and its manufacturing method
JP2006351621A (en) * 2005-06-13 2006-12-28 Honda Motor Co Ltd Bipolar semiconductor device and its manufacturing method
JP2007173841A (en) * 2005-12-22 2007-07-05 Cree Inc Silicon carbide bipolar junction transistor having silicon carbide passivation layer on base region and method of fabricating thereof
JP2007287782A (en) * 2006-04-13 2007-11-01 Hitachi Ltd Mesa bipolar transistor
JP2009054931A (en) * 2007-08-29 2009-03-12 Hitachi Ltd Bipolar element and its manufacturing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9478629B2 (en) 2010-07-14 2016-10-25 Fairchild Semiconductor Corporation Conductivity modulation in a silicon carbide bipolar junction transistor
WO2012105899A1 (en) * 2011-01-31 2012-08-09 Fairchild Semiconductor Corporation Sic bipolar junction transistor with overgrown emitter
WO2012104322A1 (en) * 2011-01-31 2012-08-09 Fairchild Semiconductor Corporation Silicon carbide bipolar junction transistor comprising shielding regions and method of manufacturing the same
US8785945B2 (en) 2011-01-31 2014-07-22 Fairchild Semiconductor Corporation SiC bipolar junction transistor with overgrown emitter
US9515176B2 (en) 2011-01-31 2016-12-06 Fairchild Semiconductor Corporation Silicon carbide bipolar junction transistor including shielding regions
JP2013041985A (en) * 2011-08-16 2013-02-28 Shindengen Electric Mfg Co Ltd Silicon carbide semiconductor device
JP2015018859A (en) * 2013-07-09 2015-01-29 国立大学法人京都大学 Semiconductor device, method of manufacturing semiconductor device, and thermal treatment apparatus

Also Published As

Publication number Publication date
JPWO2010024240A1 (en) 2012-01-26
JP5469068B2 (en) 2014-04-09

Similar Documents

Publication Publication Date Title
JP4777699B2 (en) Bipolar semiconductor device and manufacturing method thereof
JP5961865B2 (en) Semiconductor element
JP4751308B2 (en) Horizontal junction field effect transistor
US8846531B2 (en) Method of manufacturing an ohmic electrode containing titanium, aluminum and silicon on a silicon carbide surface
JP2011044688A (en) Semiconductor device and manufacturing method thereof
JP2018206873A (en) Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device
JP2015115373A (en) Semiconductor apparatus, and manufacturing method of semiconductor apparatus
JP2017092355A (en) Semiconductor device and semiconductor device manufacturing method
WO2010024243A1 (en) Bipolar semiconductor device and method for manufacturing same
JP2012160485A (en) Semiconductor device and manufacturing method of the same
JP5469068B2 (en) Bipolar silicon carbide semiconductor device and manufacturing method thereof
JP2009043880A (en) Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device
JP2013058668A (en) Semiconductor element and manufacturing method therefor
JP5470254B2 (en) Junction type semiconductor device and manufacturing method thereof
US20110095398A1 (en) Bipolar semiconductor device and method of producing same
WO2015111177A1 (en) Semiconductor device, power module, power conversion device, and railway vehicle
JP2006269679A (en) Method of manufacturing junction type semiconductor device
JP3856729B2 (en) Semiconductor device and manufacturing method thereof
JP2017199926A (en) Semiconductor device and semiconductor device manufacturing method
JP2016058660A (en) Semiconductor device
JP5514726B2 (en) Junction type semiconductor device and manufacturing method thereof
JP2005033030A (en) Semiconductor device and manufacturing method thereof
JP6233537B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2019165245A (en) Semiconductor device
JP6183234B2 (en) Semiconductor device and manufacturing method of semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09809891

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2010526712

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09809891

Country of ref document: EP

Kind code of ref document: A1