WO2004049724A1

WO2004049724A1 - Jbig arithmetic encoder

Info

Publication number: WO2004049724A1
Application number: PCT/FR2003/050124
Authority: WO
Inventors: Jean-Paul Verniere; Philippe Gautier; Bruno Paucard; David Fresneau
Original assignee: Tak'asic
Priority date: 2002-11-19
Filing date: 2003-11-19
Publication date: 2004-06-10
Also published as: AU2003295064A1; FR2847410B1; FR2847410A1

Abstract

The invention concerns an arithmetic encoding method for a hardware architecture comprising a register A containing the size of the current interval, a register C containing the lower boundary of the current interval and a register CX containing the context required for arithmetic encoding, and wherein the value contained in said register A is renormalized if it is less than a predefined value. The method is characterized in that said renormalization consists in: calculating in parallel N Ai values, each value resulting from multiplying the value contained in register A by an integer; determining the Ai value higher than said predefined value and not greater than all the Ai values higher than said predefined value; recording the Ai value determined at the preceding step in register A.

Description

JBIG ARITHMETIC ENCODER

The present invention relates to the field of digital image coding, in particular lossless image coding, one of the examples of which is the JBIG standard.

The present invention relates more particularly to the part of coding called arithmetic coding and to the coding method implemented.

The prior art already knows, by American patent application US 5668737, a parallelized arithmetic coding method making it possible to reduce the coding time. A method of high speed data computation and data compression includes an input module for receiving an input data stream from an input port. An encoder is coupled to an input module and performs arithmetic coding to encode the input data stream. An output module provides a stream of encoded data from the encoder to an output port. During the encoding process, the encoder performs a combination of parallel and serial calculation steps on the data in the input data stream. The result is that the computation cycle time for the encoding process is reduced significantly. This prior art method only concerns the part specific to arithmetic coding. This coding is appended to complementary processes which can also be parallelized. This document does not concern these annexed parts.

The prior art also knows, by the document “Parallel design of arithmetic coding” IEEE PROCEEDINGS: COMPUTERS AND DIGITAL TECHNIQUES (JIANG et AL.), A description and an implementation of an architecture parallel for arithmetic coding. The input symbols are divided into groups and processed in parallel, which increases the processing speed of the coding. This parallel coding is also implemented on VLSI using a VHDL technique. This document is concerned with arithmetic coding and its parallel processing. However, it does not at any time mention the necessary step of renormalization of the interval size registers which is the object of the present invention. Only symbol data is processed in parallel.

The prior art also knows, by the document "A parallel architecture for arithmetic coding and its VLSI implementation" CIRCUITS AND SYSTEM 1996 (HORNG-YEONG LEE et AL.), A parallel processing algorithm for the real-time implementation of coding arithmetic. The implementation includes a parallel processing matrix in the form of a tree. At each cycle, a group of input symbols can be coded, which increases the speed of arithmetic coding. This document is concerned with arithmetic coding and its parallel processing. He mentions in the third part. notion of renormalization of intervals, its principle and its usefulness. It also gives the renormalization algorithm for the interval sizes. However, this algorithm does iterative processing of the interval to be renormalized and is not processed in parallel. The parallel processing of this type of task annexed to the coding is moreover the essential object of the present invention.

The present invention intends to remedy the drawbacks of the prior art by proposing a coding method comprising a particularly optimized renormalization step. To this end, the invention relates in its most general sense to a method of arithmetic coding by a hardware architecture comprising in particular an A register containing the size of the current interval, a C register containing the lower bound of the current interval and a register CX containing the context necessary for arithmetic coding, and where the value contained in said register A is renormalized if it is less than a predefined value characterized in that said renormalization consists in

• calculate in parallel N values Ai, each value resulting from the multiplication of the value contained in register A by an integer; • determining the value Ai greater than said predefined value and less than or equal to all the values Ai greater than said predefined value;

• record the value Ai determined in the previous step in register A.

Preferably, said predefined value is 0x8000. Advantageously, said integers used to calculate the Ai are multiples of 2.

According to a particular variant, the method according to the invention further comprises a step consisting in calculating the new value of the most probable symbol (MPS) of the register CX by performing an “EXCLUSIVE OR” operation on the following two values:

• the switching value corresponding to the state of the CX register, and

• the value of the most probable symbol (MPS) of the CX register. The present invention will be better understood by means of the description, given below for purely explanatory purposes, of an embodiment of the invention, with reference to the appended figures: - Figure 1 shows the mechanism for doubling the registers A and C;

Figure 2 illustrates the process according to the invention.

A standard arithmetic coder includes a first step of interval subdivision.

The interval subdivision according to probability and recursively is the basis of arithmetic coding. Conceptually, a sequence of input symbols is associated with a real number x over the interval (0,1) where the bracket at the end of an interval means that the extreme value is included and the parenthesis means that the value extreme is excluded. We no longer transmit the original sequence but the binary expression of x. The portion of (0,1) in which it is known that x is located after coding an initial sequence of symbols is called the current coding interval. For each binary input, the current coding interval is divided into two sub-intervals, the sizes of which are proportional to the relative probabilities of the occurrences of each value for the symbol. The new current coding interval is the subinterval associated with the value actually assigned to the symbol. In an encoder, the knowledge of the current coding interval is contained in a variable giving its size and a variable giving its base (smallest value). The output flow is obtained by the variable giving the base.

In the partition of the current interval into two subintervals, the subinterval for the symbol le least likely (LPS) is placed above the sub-range for the most likely symbol (MPS). Thus, when the LPS is coded, the MPS subinterval is added to the base. This coding convention requires that the symbols be recognized as either MPS or LPS and not as 0 or 1. Therefore, the size of the LPS interval and the meaning of the MPS for each symbol must be known to encode said symbol.

Since the code stream always points to a real number in the current coding interval, the decoding process relates to the question of determining, at each decision, which subinterval is pointed to by the coded chain. This is also done recursively using the same interval subdivision process as in the encoder. Each time a decision is decoded, the decoder subtracts from the code stream each interval added by the coder. Thus, the code stream in the decoder is a pointer to the current interval relative to the base of the current interval. Since the coding process involves the addition of binary fractions rather than the concatenation of entire code words, the most likely binary decisions can often be coded at a cost of less than one bit per decision. It is possible to carry out these coding operations using the arithmetic of integers with fixed precision. A register contains the size of the current coding interval and this register is normalized so that it is always contained in the interval [0x8000,0x10000] where the prefix "Ox" characterizes a hexadecimal integer. If the result of the encoding of a symbol A temporarily falls below the value 0x8000, the said result is doubled the number of times necessary for it to be greater than or equal to 0x8000. These doublings are called "renormalizations". A second register C contains the bits of the code stream corresponding to the preceding interval decisions. The C register is also doubled each time the A register is doubled. To avoid congestion in the C register, a byte is periodically removed, said byte being composed of the most significant bits of C and placed in an external buffer memory. The content of this buffer cannot be sent without any carryover carryovers being made.

The doubling mechanism of registers A and C usually used is illustrated in Figure 1. In this usual mechanism, the loop should be repeated as many times as necessary, which can be time-consuming, especially when the interval chosen at previous step is that corresponding to the LPS, because it is then of reduced size compared to the interval which preceded it. In order to avoid the cost of time, which can be significant and which is above all uncontrolled, the method according to the invention proposes to parallelize this step in order to guarantee a maximum number of clock strokes for carrying it out.

The method according to the invention, illustrated in FIG. 2, uses an architecture comprising a plurality of calculation modules placed in parallel with respect to the incoming data stream. The value of register A is supplied as input to each of said modules, simultaneously. Each calculation module performs the calculation for which it is programmed and provides a result Ai. The operations performed by the calculation modules are preferably a multiplication of the register A by an integer. In the case of a JBIG arithmetic coding, each calculation module performs a multiplication of the register A by a multiple of 2. We thus obtain N values Ai. A standard logical operator makes it possible to determine what is the minimum value Ai, greater than threshold predefined by the user. Said threshold is “0x8000” in the case of a JBIG arithmetic coding. The determined value Ai is assigned to the new register A. The operation carried out on register A by the module which provided the chosen value Ai is carried out again on said register C.

The method according to the invention uses a CX register which contains the context necessary for arithmetic coding. We then define the state of the register: ST [CX]. This state is a value between 0 and 113 and is coded on seven bits. Each state ST [CX] of the register CX corresponds to a switching value SWTCH [ST [CX]]. If S TCH [ST [CX]] is 1, MPS [CX] is inverted.

The invention is described in the foregoing by way of example. It is understood that a person skilled in the art is able to carry out different variants of the invention without going beyond the scope of the patent.

Claims

1. Method of arithmetic coding by a hardware architecture comprising in particular an A register containing the size of the current interval, a C register containing the lower bound of the current interval and a CX register containing the context necessary for the arithmetic coding, and where the value contained in said register A is renormalized if it is less than a predefined value, characterized in that said renormalization consists in:

• record the value Ai determined in the previous step in register A.

2. Arithmetic coding method according to claim 1, characterized in that said predefined value is 0x8000.

3. Arithmetic coding method according to claim 1 or 2, characterized in that said integers used to calculate the Ai are multiples of 2.

4. Method of arithmetic coding according to one of the preceding claims, characterized in that it also comprises a step consisting in calculating the new value of the most probable symbol (MPS) of the register CX by carrying out an "EXCLUSIVE OR" operation on the following two values:

• the switching value corresponding to the state of the CX register, and “the value of the most probable symbol (MPS) of the CX register.