WO1988004074A1

WO1988004074A1 - Circuit for monitoring a pulse train

Info

Publication number: WO1988004074A1
Application number: PCT/DE1987/000522
Authority: WO
Inventors: Bernhard Mattes; Wolfram Neth; Hartmut Schumacher; Hartmut Seiler
Original assignee: Robert Bosch Gmbh
Priority date: 1986-11-26
Filing date: 1987-11-16
Publication date: 1988-06-02
Also published as: KR890700245A; DE3640351C2; DE3640351A1

Abstract

Circuit for monitoring a pulse train (P) comprising an input stage (K1) to which are fed the pulses to be monitored, and circuit means in order to determine the presence of a pulse of said train. If in a predeterminable time interval no pulse is observed in the circuit input stage, an output stage of said circuit is activated which provides an output pulse train (BR) and an error signal (ER).

Description

Circuit arrangement for monitoring a pulse train

State of the art

The invention relates to a circuit arrangement for monitoring a pulse train in accordance with the preamble of the main claim. For monitoring the function of electronic circuit arrangements in which pulse sequences occur, in particular in microprocessors, circuit arrangements are already known which check whether a pulse is generated at an output of the electronic circuit arrangement provided for monitoring. Such monitoring circuits are also referred to as a "watch-dog circuit". A pulse of a pulse sequence recognized by the monitoring circuit resets the electronic circuit arrangement to its initial state and the process of monitoring and resetting takes place again. If no more pulses are generated, this is recognized by the monitoring circuit after the intended monitoring time has elapsed and interpreted as a malfunction of the electronic circuit arrangement. In this case, the monitoring circuit generates periodic reset signals for the electronic circuit arrangement and an error signal for actuating emergency running and / or warning devices. When using a microprocessor, the pulses generated by the electronic circuit arrangement and monitored by the monitoring circuit generally arise because the microprocessor periodically executes a test program. A disadvantage of previously known monitoring circuits is that they only detect the absence of pulses from a pulse sequence, but do not determine if too many pulses are being generated, for example by skipping commands in the program routine or the output of the electronic circuit arrangement to be monitored in time with the microprocessor oscillator swings.

Advantages of the invention

The circuit arrangement according to the invention with the features of the main claim has the advantage of a considerably improved monitoring possibility compared to the known monitoring circuit, since malfunctions of the electronic circuit arrangement can also be recognized, which are expressed in an excessively high pulse repetition frequency. This in turn can significantly increase the reliability of the electronic circuit arrangement, which is of particular importance if it is used in safety devices for vehicle occupants.

Advantageous further developments and improvements of the circuit arrangement specified in the main claim are possible due to the features listed in the subclaims. Their advantages result from the description and drawing of the exemplary embodiment. drawing

An embodiment of the invention is shown in the drawing and explained in more detail in the following description. FIG. 1 shows a circuit arrangement for monitoring a pulse sequence, FIG. 2 shows pulse diagrams as they occur at special points in the circuit arrangement of FIG. 1, and FIG. 3 shows the use of the circuit arrangement in a safety device for vehicle passengers.

Description of the embodiment

The circuit arrangement according to the invention recognizes whether the clock frequency or the period T of a pulse sequence deviates upwards or downwards from a predetermined value. If a deviation is found, i.e. if the period T is outside a tolerance interval with the limits TU and TO, the circuit arrangement emits two output signals, namely an output pulse sequence BR and a continuous signal ER. Both types of signals are emitted as long as the clock frequency of the monitored pulse train deviates from the specified setpoint.

The function of a microprocessor can be monitored particularly expediently with the circuit arrangement according to the invention. The output pulse train BR serves as a reset signal for the microprocessor. The continuous signal ER can advantageously control an emergency running or warning device, which indicate a malfunction of the electronic circuit arrangement and put additional emergency functions into operation. This is particularly important in the case of safety devices for vehicle occupants, since they are dependent on the absolute reliability of the safety devices and must immediately recognize malfunctions that have occurred.

For this purpose, the monitoring circuit comprises circuit means which determine the pulse spacing or the period T of the pulse sequence P supplied to the input stage of the monitoring circuit and which cause the output stage of the monitoring circuit to emit the signals already mentioned if the pulse intervals lie outside a predefinable time interval. In order to determine the pulse spacing of the pulse sequence P present at the input stage K1, the circuit arrangement comprises a charge store C1, which is connected to an operating voltage source UB via a series resistor R1 and is charged by the latter. Pulses of the pulse sequence P present at the input stage K1 of the monitoring circuit cause the charge store Cl to be rapidly discharged up to a first threshold value S2. After this rapid discharge, the charge store C1 is charged via the series resistor R1 with a predefinable time constant, the charge voltage passing through a second threshold value S4 after a time TU, which determines the lower limit value of the predefinable time interval. If the pulse interval T becomes too large or the pulses P at the input stage K1 of the circuit arrangement are completely absent, the charge store C1 can continue to charge until a third threshold value S3 is reached, which defines the upper tolerance limit TO of the predefinable time interval. S3 is expediently about 1-2 below the operating voltage UB. When this upper switching threshold S3 is reached, a comparator K3 switches which controls a circuit group, which consists of OR3, FF4, K5, C2 and the transistor T2 and acts as a monostable multivibrator, which outputs the output signal BR. The one at the exit

the inverted flip-flop FF4 pending inverted output signal BR fed back and then independently of the input signal P via NOR5, FF2, FF1 a discharge of the charge storage C1, whereby the monitoring circuit switches to oscillator operation and emits pulses BR periodically at time interval TO via the output stage. These also set a further bistable multivibrator FF5 via a NOR gate NOR4, at the output thereof

the output signal ER is present, which can be used, for example, to give an alarm and / or to activate emergency means. The above-mentioned state of the circuit arrangement is only ended when the pulse S3 with the period T at the input stage K1 of the circuit arrangement is no longer reached by pulses P with the period T and therefore no more pulses BR are generated by the output stage.

The way in which the circuit arrangement monitors that the pulse interval of the pulse sequence supplied to the input stage lies within a predeterminable time interval is now explained with reference to the pulse diagrams in FIG. It is initially assumed that the period of the input pulses P lies within a lower limit TU and an upper limit TO. The pulse sequence supplied to the input stage with the pulses P is shown in FIG. 2a. Each trailing edge of an input pulse P starts the discharge of the charge storage C1 connected to the operating voltage UB via R1. The discharge is complete when a lower threshold S2 is reached, at which the comparator K2 switches and at which the cooperating bistable flip-flops FF2 and FF1 block the switching element T1 which short-circuits the charge storage device C1. This lower threshold S2 is expediently in a range from approximately 0.2 V to 0.3 V. After reaching the lower threshold S2 and blocking the switching element T1 via K2, FF2 and FF1, the charge store C1 can use the series resistor R1 to determine a certain value Reload time constant. When an average threshold S4 is reached, the comparator K4 switches and sets the bistable flip-flop FF3 back so that the

-Output of the bistable flip-flop FF3 output signal "high" and the output signal at the subsequent NOR gate NOR2 assumes the value "low". Appropriate values for the middle threshold 4 are in the voltage range around 0.5 UB. The signal curve at point 3 of the circuit arrangement, ie on

The output of the bistable multivibrator FF1 is shown in FIG. 2c, the signal curve at the output of the comparator K4 is shown in FIG. 2d.

The charging of the charge store C1 via the series resistor R1 now continues until a new pulse P is present at the input stage K1 of the circuit arrangement and again initiates a new discharge of the charge store C1 with its trailing edge. As soon as the mean threshold S4 is again undershot during this new discharge process, the output signal present at the output of the comparator K4 goes back to "low" (see FIG. 2d) and gives both the reset input R and the set input S of the bistable flip-flop FF3 free. The previous switching state of this bistable multivibrator FF3 - the output signal on it

-Output was "high" - (see pulse diagram in FIG. 2f) is initially retained, so that the output of NOR2 is kept low. The result of this is that the OR gate OR3 is not activated and the bistable flip-flops FF4 and FF5 maintain their switching state. No output signals BR and ER are thus emitted from the output stage of the circuit arrangement. If the charge storage C1 is discharged again to the lower threshold S2, as already described above, the switching element T1 is blocked again, and the signal level at the switching point 3, that is to say at the Q output of the bistable flip-flop FF1, assumes the value "low". As a result, the bistable multivibrator FF3 is set via a NOR gate NOR1, that is, on

The output of this flip-flop signal (see pulse diagram in FIG. 2f) assumes the "low" level. A precondition for a correct functioning of the circuit arrangement is that the signal level "high" is present at point 3a of the circuit arrangement (see pulse diagram FIG. 2e) somewhat earlier than the signal level "low" at point 5 of the circuit arrangement Circuit arrangement, that is to say at the output of the bistable multivibrator FF3 (see pulse diagram in FIG. 2f). This is ensured in the exemplary embodiment of the circuit arrangement in that a larger number of circuit elements is arranged in the signal path up to point 5 of the circuit arrangement. Furthermore, the storage time of the transistors in the NOR gate NOR2 also contributes to the signal delay required here.

It is now assumed that the period T is smaller than the lower limit TU of the predeterminable time interval. In this case, the output of K4 remains low, which means that Ü from FF3 also maintains its previous low level. A high signal occurring at point 3 thus triggers the output signals BR and ER of the output stage of the circuit arrangement via INV1, the NOR gate N0R2 and via the OR gate OR3. For this purpose, the bistable multivibrator FF4 is set via an input signal from OR3 located at its set input S, ie BR = "high" and signal level at

-Output of the flip-flop flip-flop FF4, or at node 7 of the

Circuit arrangement = "low" - and releases the charging of a second charge storage device T2 via the switching element T2. As soon as a threshold S5 is reached during the charging process of the charge store C2, a comparator K5 switches to a further, lower threshold S6 (hysteresis) and thus resets the bistable flip-flop via its reset input R, so that the output signal BR reaches the level assumes "low". The pulse duration of the output signal BR is thus determined by the charging time of the charge store C2 (monoflop function). As soon as the voltage at the charge store C2 has fallen below the threshold value S6 again, the comparator K5 switches back to the first threshold value S5 and releases the bistable flip-flop again so that a new BR pulse can be started. The BR pulses are thus clocked at the input stage. the pulses P applied to the circuit arrangement. If the input pulses P come in shorter time intervals than the monoflop time, a new output pulse BR only arises when the monoflop time has expired and the signal level at the output of OR3 is again "high". The monitoring circuit described above thus makes it possible to determine whether the period T of a pulse sequence P present at the input stage K1 of the circuit arrangement lies within the limits TU and TO of a predefinable time interval. If this is not the case, ie the period T lies outside this interval (T <TU, or T> TO), output signals BR or ER are output by the output stage of the circuit arrangement. The time measurement of the period T takes place via the charging voltage applied to a charge storage device C1. During the charging process of the charge store, a voltage threshold S4 is exceeded after the time TU. This is stored with priority (NOR gate NOR1) in a bistable flip-flop FF3. The next pulse of the pulse sequence P present at the input stage K1 of the circuit arrangement starts the discharge pulse with its trailing edge (see pulse diagram according to FIG. 2c) for the charge store C1 and this serves simultaneously as a clock pulse for querying those stored in the bistable flip-flop FF3 Information. The latter decides on her

Output lying output signal (see pulse diagram at point 5 of the circuit arrangement according to Figure 2f) and the output signal at the NOR gate NOR2 (see pulse diagram at point 6 of the circuit arrangement according to Figure 2g) whether the output stage of the circuit arrangement generates output pulses BR or not. The output elements of the circuit arrangement include the circuit elements FF4, K5, T2, C2, which act as a monostable multivibrator. A pulse BR emitted by the output stage sets a further bistable flip-flop FF5, which supplies a further output signal ER. The bistable flip-flop FF3 is reset for the next evaluation of the period T when the pulse at switching point 3 (see pulse diagram according to FIG. 2c) has ended. A special reset pulse is therefore not necessary. If the period T is again within the predetermined time interval, the bistable flip-flop FF5 is also reset again, at its output connection

the output signal ER was pending. The reset is carried out by the output signal of the NOR gate N0R4 present at the reset input R of the bistable multivibrator FF5, with the three inputs of which three signals are linked, namely the output signal BR of the bistable multivibrator FF4, output signal on

Output of the bistable multivibrator FF3 and output signal of the inverter INV1 (signal form according to FIG. 2e), which in this case only have the signal level "low" at the same time. The circuit arrangement is particularly expediently used in safety devices for vehicle occupants, in which the reliability requirements are particularly high. This is explained schematically with reference to FIG. 3, in which a vehicle 30 with an occupant 31 is shown. The safety device for protecting the occupant 31 includes restraint means, such as, for example, a seat belt 33 with a belt tensioner and an airbag 34, which, in the event of an emergency, hold the vehicle occupant 31 in a safe position in the seat or protect it from facial injuries. The belt 33 and the airbag 34 are activated by a safety device 32 arranged in the vehicle 30, which includes acceleration sensors and a circuit device for evaluating the signals emitted by the acceleration sensors.

Claims

Expectations

1.Circuit arrangement for monitoring a pulse train with an input stage, to which the pulses to be monitored are supplied, with circuit means for determining the presence of a pulse of the pulse train, and with an output stage which, in the absence of a pulse, emits an error signal on the one hand and an output pulse train on the other characterized in that circuit means are provided which determine the pulse interval of the pulse sequence supplied to the input stage and which also cause the output stage to emit an error signal and an output pulse sequence if the pulse interval is outside a predeterminable time interval.

2. Circuit arrangement according to claim 1, characterized in that the circuit means for determining the pulse spacing of the pulse sequence applied to the input stage (K1) comprise a charge store (C1) which can be charged via a series resistor (RT) from a voltage source (ÜB) and which by, a pulse (P) of the pulse train present at the input stage (K1) is at least partially discharged.

3. Circuit arrangement according to one of claims 1 and 2, characterized in that the output stage comprises a monostable multivibrator (OR3, FF4, K5, C2) which is controllable from the output terminal of a comparator (K3) in the absence of a pulse within a definable time interval and emits an output pulse train (BR).

4. Circuit arrangement according to one of claims 1 to 3, characterized in that three switching thresholds (S2, S3, S4) are predetermined by the circuit means for the voltage present at the charge store (C1), wherein

a) when the lowest switching threshold (S2) is reached, the discharge process of the charge feeder (C1) is ended;

b) when the middle switching threshold (S4) is reached a bistable flip-flop (FF3) is reset (i.e. Q of FF3 assumes signal level "high";

c) and when the upper switching threshold (S3) is reached or the middle holding threshold (S4) * is not reached, the monostable multivibrator (OR3, FF4, K5, C2) is activated.

5. Circuit arrangement according to one of claims 1 to 4, characterized in that for detecting the switching thresholds (S2, S3, S4) comparators (K2, K3, K4) are used.

6. Circuit arrangement according to one of claims 1 to 5, characterized in that the following conditions apply to the switching thresholds (S2, S3, S4):

0.1V <S2 <0.3V

S4 about 0.5. Practice

S3 <UB-2V.

7. Circuit arrangement according to one of claims 1 to 6, characterized in that a switching element (T1) is connected in parallel to the charge store (C1), which short-circuits the charge store (C1) in the event of discharge.

8. Circuit arrangement according to one of claims 1 to 7, characterized in that the switching element (T1) is a transistor, the collector-emitter path is connected in parallel to the charge storage device (C1), and the base connection with the Q output of a first bistable Flip-flop (FF1) is connected, the reset input (R) is connected to the output (Q) of a second bistable flip-flop (FF2), the set input (S) is connected to the output of the comparator (K2), which at Reaching the switching threshold (S2) switches.

9. Use of the circuit arrangement according to one of claims 1 to 8 in a safety device for vehicle occupants.

* Note: The evaluation at threshold S4 is the essence of the invention.