US20140084977A1 - Wide Frequency Range Delay Locked Loop - Google Patents
Wide Frequency Range Delay Locked Loop Download PDFInfo
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- US20140084977A1 US20140084977A1 US14/092,788 US201314092788A US2014084977A1 US 20140084977 A1 US20140084977 A1 US 20140084977A1 US 201314092788 A US201314092788 A US 201314092788A US 2014084977 A1 US2014084977 A1 US 2014084977A1
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- 230000003111 delayed effect Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000000630 rising effect Effects 0.000 description 27
- 239000000872 buffer Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 230000001419 dependent effect Effects 0.000 description 6
- 238000001514 detection method Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000008014 freezing Effects 0.000 description 1
- 238000007710 freezing Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
Definitions
- SDRAM synchronous dynamic random access memory
- microprocessors receive an external clock signal generated by an external clock source such as a crystal oscillator.
- the external clock signal received through an input pad on the device is routed to various circuits within the device through a tree of buffer circuits.
- the buffer tree introduces a common delay between the external clock and each buffered clock.
- a delay locked loop with an adjustable delay line is used to synchronize the buffered clock signal with the external clock signal by delaying the external clock signal applied to the buffer tree.
- the DLL includes a phase detector, which detects the phase difference between the external clock signal and a buffered clock signal. Based on the detected phase difference, the DLL synchronizes the buffered clock signal to the external clock signal by adding an appropriate delay to the external clock signal until the buffered external clock signal (the internal clock) is in phase with the external clock signal.
- the DLL can be implemented as an analog delay locked loop or a digital delay locked loop. In an analog delay locked loop, a voltage controlled delay line is used to delay the external clock signal.
- FIG. 1 is a block diagram of a prior art analog delay locked loop (DLL) 100 .
- the analog DLL 100 synchronizes an internal clock signal CK I with an external clock signal CK E .
- the external clock CK E signal is coupled to a voltage controlled delay line 102
- the voltage controlled delay line 102 is coupled to clock tree buffers 108 .
- the delayed external clock signal CK E is fed into the clock tree buffers 108 where it propagates to the outputs of the tree and is applied to the various circuits.
- the delay through the clock tree buffer 108 results in a phase difference between the external clock signal CK E and the internal clock signal CK I .
- the voltage controlled delay line 102 adds further delay to the external clock signal CK E to synchronize the external and internal clock signals.
- one of the outputs of the clock tree buffers 108 is coupled to a phase detector 104 where it is compared with the external clock signal CK E .
- the phase detector 104 detects the phase difference between the internal clock CK I and the external clock CK E .
- the output of the phase detector 104 is integrated by a charge pump 106 and a loop filter capacitor 112 to provide a variable bias voltage V CTRL 110 for the voltage controlled delay line (VCDL) 102 .
- the bias voltage V CTRL selects the delay to be added to the external clock signal by the VCDL 102 to synchronize the internal clock signal CK I with the external clock signal CK E .
- the phase detector 104 can be a D-type flip-flop with the D-input coupled to the external clock signal CK E and the clock input coupled to the internal clock signal CK I . On each rising edge of the internal clock signal CK I , the output of the phase detector 104 indicates whether the rising edge of the internal clock signal is before or after the rising edge of the external clock signal.
- the analog DLL 100 produces a voltage controlled delay with high accuracy. However performance of the analog DLL varies over a frequency range because of a non-linear control voltage characteristic.
- FIG. 2 is a graph illustrating the non-linear control voltage characteristic for the voltage controlled delay line shown in FIG. 1 .
- devices support a wide range of external clock frequencies within which an operational frequency is selected for a particular device.
- the device can operate at any frequency between point A and point C.
- the operational frequency selected is at point B.
- control voltage characteristic is non-linear: sharp at one end of the control voltage range (point C) and almost flat at the opposite end (point A). This control voltage characteristic results in DLL instability at point C and long lock times at point A.
- the wide range of frequencies (delays) is controlled by the bias voltage V CTRL .
- the bias voltage V CTRL is the output of the charge pump 106 , which remains in a high-impedance state most of the time. Any noise on the bias voltage signal V CTL disturbs the output of the analog DLL 100 .
- a small voltage change ( ⁇ V) due to noise results in a large change in delay.
- the analog DLL is very sensitive to noise when operating at point B, within the wide frequency range shown from point C to point A. Therefore, the analog DLL is not stable within a wide frequency range.
- a digital DLL does not have the stability problem of an analog DLL.
- the accuracy of a digital DLL is not the same as the accuracy of an analog DLL, because the delay is provided by combining fixed quantum (steps) of delay.
- a decrease in step size results in a corresponding increase in silicon area because more delay elements are required to cover the wide frequency range.
- a delay locked loop which has high accuracy, good stability and a fast lock time over a wide frequency range is presented.
- the delay locked loop combines shorter lock time, good accuracy and stability with low power consumption and small silicon area for the delay locked loop operating in a wide range of frequencies.
- the delay locked loop includes a digital delay circuit and an analog delay circuit.
- the digital delay circuit engages delay elements to provide coarse phase adjustment in the delay locked loop.
- the analog delay circuit provides a fine phase adjustment in the delay locked loop while the digital delay circuit is held at a fixed delay.
- a lock detector in the digital delay circuit detects completion of the coarse phase adjustment, freezes the fixed delay upon completion and enables fine phase adjustment.
- the digital delay circuit which includes a plurality of fixed delay elements, operates in a wide delay range.
- the analog delay circuit operates in a small delay range within the wide delay range and is held at a second fixed delay until the digital delay circuit completes the coarse phase adjustment.
- FIG. 1 is a block diagram of a prior art analog delay locked loop (DLL);
- DLL delay locked loop
- FIG. 2 is a graph illustrating the non-linear controlling voltage characteristic for the voltage controlled delay line shown in FIG. 1 ;
- FIG. 3 is a block diagram of a wide frequency range delay locked loop according to the principles of the present invention.
- FIGS. 4 , 4 A and 4 B illustrates delay cells in the DCDL and the VCDL
- FIG. 5 is a schematic of one embodiment of any one of the delay cells shown in FIG. 4 ;
- FIG. 6 is a graph illustrating the non-linear controlling voltage characteristic for the narrow frequency range of the VCDL in the DLL shown in FIG. 3 ;
- FIG. 7 is a schematic of an embodiment of the lock detector and the analog switch shown in FIG. 3 ;
- FIGS. 8A-C are timing diagrams illustrating the relationship of the phase detector output to the phase difference between the clocks.
- FIG. 9 is a timing diagram illustrating signals in the schematic shown in FIG. 7 .
- FIG. 3 is a block diagram of a wide frequency range delay locked loop (DLL) 300 according to the principles of the present invention.
- the wide frequency range DLL 300 has two domains of operation: a digital domain which includes a digital delay circuit 302 and an analog domain which includes an analog delay circuit 304 .
- the wide frequency range DLL 300 combines the two techniques to provide high accuracy, good stability and a fast lock time over a wide frequency range.
- the digital delay circuit 302 is responsible for coarse phase adjustment during initialization and the analog delay circuit 304 is responsible for fine phase adjustment during normal operation, after coarse phase adjustment is completed by the digital delay circuit 302 .
- the digital delay circuit 302 operates within the wide delay range and brings the delay locked loop 300 to a stable operation point during power-up initialization.
- the analog delay circuit 304 operates within a small delay range of the stable operation point within the wide delay range and maintains the delay locked loop at the stable operation point while the digital delay circuit 302 is held at a fixed delay.
- the overall delay provided by the DLL includes a digitally controlled delay line (DCDL) 306 having a set of delay elements, each having a fixed delay and a voltage controlled delay line (VCDL) 312 .
- DCDL digitally controlled delay line
- VCDL voltage controlled delay line
- the combination of the DCDL delay provided by the DCDL 306 and the VCDL delay provided by the VCDL 312 provides an accurate delay. Only one of the domains can vary the DLL delay at any time.
- the digital delay circuit 302 varies the DCDL 306 (coarse delay). After coarse phase adjustment is complete (lock is reached), the DCDL delay is held at a fixed number of DCDL delay elements (frozen) and the analog delay circuit 304 varies the DLL delay to provide fine phase adjustment by varying the VCDL delay.
- the digital delay circuit 302 operates within the wide delay range to bring the DLL 300 to the operation point (lock) quickly to provide a short lock time.
- a lock detector 310 in the digital delay circuit 302 detects when the digital delay circuit 302 has brought the DLL delay to the stable operation point and enables control of the DLL delay to be switched to the analog delay circuit 304 .
- a phase detector 320 detects the phase difference between the external clock signal CK E and the internal clock signal CK I .
- the phase detector 320 can be any phase detector well known to those skilled in the art.
- the phase detector 320 ( FIG. 3 ) includes a D-type flip-flop with CK I connected to the clock input and CK E connected to the D-input. The rising edge of CK I latches the state of CK E at the output (Ph_det) of the D-type flip-flop.
- the analog delay circuit 304 includes a multiplexor 314 , a VCDL 312 and a charge pump 316 .
- the VCDL 312 is a chain of differential-input-differential-output stages (delay elements) with voltage control.
- the multiplexor 314 selects the source of the VCDL bias voltage 322 to the VCDL 312 .
- the VCDL bias voltage 322 is a fixed bias voltage V BPI , V BNI provided by bias voltage generator 318 or a variable bias voltage V BP2 , V BN2 provided by charge pump 316 .
- differential bias voltage V BPI , V BNI provides the VCDL bias voltage 322 through multiplexor 314 .
- the VCDL bias voltage 322 provides a constant VCDL delay. That delay may be in the middle of the full delay range of the VCDL to enable fine tuning in both positive and negative directions as discussed below.
- the code stored in a counter 308 is initialized to zero, which corresponds to the minimum delay; that is, the minimum number of delay cells in the DCDL 306 that are engaged.
- the lock detector 310 allows the DCDL 306 to increase the DCDL delay by adding delay cells as the counter 318 is incremented until the nearest rising edge of the internal clock signal CK I is aligned with the external clock signal CK E .
- the counter 308 is incremented by the external clock signal CK E until lock is reached (the clocks are aligned).
- the counter 308 is an up counter which increments on each rising edge of the external clock signal CK E while enabled by the SW signal from the lock detector 310 .
- Delay cells in the DCDL 306 are added to the DCDL delay line based on the n-bit count value output by the counter 308 to engage the minimum number of DCDL delay cells necessary dependent on the bias voltage V BP1 , V BN1 .
- the SW signal output by the lock detector 310 disables any further incrementing of the counter 308 .
- the VCDL bias voltage 322 is provided by bias voltage V BP2 , V BN2 , the output of charge pump 316 , through multiplexor 314 .
- the charge pump 316 can be any charge pump well known to those skilled in the art.
- the overall delay line is minimum length to minimize noise.
- the digital delay circuit 302 is held at a fixed delay by disabling further incrementing of the counter 308 .
- Only the VCDL portion of the DLL delay line can be varied by the analog delay circuit 304 .
- the analog delay circuit 304 fine tunes the DLL delay to compensate for all drifts and condition changes to keep the external and internal clock signal edges aligned, by varying the VCDL delay, which is added to the fixed delay provided by the DCDL.
- the analog controlled delay line 310 varies the VCDL delay up or down by varying the bias voltage to the VCDL delay cells 402 based on detected phase difference between the clocks.
- FIG. 4 illustrates delay cells in the DCDL and the VCDL.
- the digitally controlled delay line (DCDL) includes a chain of DCDL delay cells 400 and the voltage controlled delay line (VCDL) includes a chain of VCDL delay cells 402 .
- the delay of each DCDL cell 400 is fixed by permanently connecting the bias voltage for each DCDL cell 400 to a fixed bias voltage V BP1 , V BN1 .
- the fixed bias voltage V BP1 , V BN1 is provided by a bias voltage generator 318 ( FIG. 3 ) which can be any type of voltage stabilizing device, for example, a band-gap reference and need not correspond to the VCDL bias voltage 322 initially applied to the VCDL.
- the DLL delay includes only the fixed delay provided by demultiplexor 404 , multiplexor 408 and the VCDL delay elements 402 in the VCDL connected to the fixed bias voltage V BP1 , V BN1 .
- the VCDL delay provided by VCDL is dependent on the fixed bias voltage V BP1 , V BN1 .
- the DCDL delay cells 400 and the VCDL delay cells 402 are the same delay cell with voltage controlled delay. However, in an alternate embodiment, the DCDL delay cell 400 can differ from the VCDL delay cell 402 .
- the DCDL is initially variable by increasing the number of DCDL delay elements 400 with each DCDL delay element 400 having the same delay fixed by the fixed bias voltage V BP1 , V BN1 .
- the same fixed bias voltage V BP1 , V BN1 is coupled to the DCDL delay elements 400 and the VCDL elements 402 .
- the fixed bias voltage coupled to the VCDL delay elements 402 and the DCDL delay elements 400 can be different; for example, a first bias voltage may be set to 0.7V DD coupled to the DCDL and a second bias voltage may be set to 0.5V DD coupled to the VCDL.
- the VCDL delay is initially fixed with each of the three VCDL delay elements 402 numbered 1-3 coupled to the fixed bias voltage V BP1 , V BN1 , but the VCDL delay varies with changes in the VCDL bias voltage 322 during normal operation.
- the number of engaged elements in the DCDL 306 is dependent on the n-bit count 406 output by the counter 308 .
- the n-bit count 406 is coupled to the de-multiplexor 404 to select the output of the de-multiplexor 404 through which the external clock is output to the DCDL 306 .
- the n-bit count 406 is also coupled to multiplexor select logic 430 which provides an m-bit multiplexor select signal, with one of the m-bits coupled to each multiplexor in the DCDL 306 .
- the multiplexor select logic 430 is a decoder which decodes the n-bit count to provide the m-bit multiplexor select signal. In the embodiment shown m is 7 and n is 3.
- the multiplexor select logic 430 decodes a three bit count 406 to select one of the seven multiplexors through which to forward the external clock as shown in Table 1 below.
- the Most Significant Bit (MSB) of the seven bit multiplexor select signal corresponds to the select signal for multiplexor 420 and the Least Significant Bit (LSB) of the seven bit multiplexor signal corresponds to the select signal for multiplexor 408 .
- MSB Most Significant Bit
- LSB Least Significant Bit
- the multiplexor select logic can be implemented as a shift register clocked by the external clock and enabled by the SW signal.
- the external clock signal CK E is delayed through DCDL delay elements engaged dependent on the n-bit count output by counter 308 .
- Control of the DLL delay is switched to the VCDL 312 by switching the bias voltage V BP1 , V BN1 to the bias voltage V BP2 , V BN2 through the multiplexor 314 ( FIG. 3 ).
- the DLL delay includes minimum delay provided by the engaged DCDL delay elements 400 in the DCDL 306 and additional delay provided by the VCDL 312 to provide an accurate DLL delay.
- the stability of the DLL is increased by using the digital domain to cover a wide delay range to obtain a minimum delay, then freezing the digital domain to allow the analog domain to operate within a small delay range to control the DLL delay.
- the bias voltage coupled to the VCDL bias voltage 322 is set so that the VCDL does not control the DLL delay until after lock is detected by the digital domain. Before lock, the VCDL merely provides a constant delay independent of the phase difference between the clocks.
- the de-multiplexor 404 directs the external clock CLK E to engage delay elements dependent on the n-bit count 406 output by the counter 308 . With count 406 set to ‘0’, CLK E is directed through output 422 of de-multiplexor 404 coupled to multiplexor 408 and no delay DCDL elements 400 are engaged.
- CLK E is directed through output 424 of the de-multiplexor 404 by count 406 set to ‘1’ to engage DCDL delay stage labeled 4.
- Multiplexor 410 is enabled to allow CLK E through to DCDL delay stage 400 labeled 4 and the m-bit multiplexor select signal output by multiplexor select logic 430 allows delayed CLK E through multiplexor 408 to the VCDL.
- All six DCDL delay stages are engaged when the count 406 is six, and CLK E is directed through de-multiplexor output 426 through multiplexors 420 , 418 , 416 , 414 , 412 , 410 , 408 and delay elements labeled 9-4.
- the DCDL line is frozen when the counter 308 is disabled by the SW signal.
- FIG. 5 is a schematic of one embodiment of any one of the delay elements shown in FIG. 4 .
- the delay cell 400 includes a source-coupled pair of NMOS devices T 1 , T 2 with symmetric loads 500 , 502 .
- the differential input clock signal CLK E I ⁇ , CLK E I+ is coupled to the respective gates of NMOS devices T 1 , T 2 with CLK E I+ coupled to the gate of NMOS device T 1 and CLK E I ⁇ coupled to the gate of NMOS device T 2 .
- the differential output clock signal CLK E O ⁇ , CLK E O+ is coupled to the respective drains of NMOS devices T 1 , T 2 .
- the sources of NMOS devices T 1 and T 2 are coupled and are also coupled to the drain of NMOS current source T 3 .
- NMOS current source T 3 compensates for drain and substrate voltage variations.
- Symmetric load 500 includes a diode-connected PMOS device T 4 connected in parallel with a biased PMOS device T 5 .
- Symmetric load 502 includes a diode-connected PMOS device T 7 connected in parallel with a biased PMOS device T 6 .
- the effective resistance of the symmetric loads 500 , 502 changes with changes in the bias voltage V BP1 resulting in a corresponding change in delay through the delay stage from the differential clock input to the differential clock output.
- FIG. 6 is a graph illustrating the non-linear control voltage characteristic for the narrow delay range of the VCDL 312 in the DLL 300 shown in FIG. 3 .
- the digital domain provides the minimum delay to bring the operating range of the DLL 300 to point B.
- the analog domain operates within a narrow delay range 600 from point B-High to point B-Low.
- This delay range is much smaller than the wide delay range supported by the DLL, but may be controlled by the same large voltage range as applied in the pure analog case of FIG. 2 .
- the small delay range controlled by a large voltage range ensures the stability of the analog domain during normal operation of the DLL.
- the analog delay circuit 304 operates within the delay range 85 ns to 80 ns over voltage range 200 mV to 800 mV. In contrast to the wide delay range over the same voltage range shown in FIG. 2 , a small variation in control voltage ( ⁇ V) does not substantially affect the delay.
- FIG. 7 is a schematic of an embodiment of the lock detector 310 and the multiplexor 314 shown in FIG. 3 .
- the lock detector 310 includes two SR flip-flops 700 , 702 , AND gate 706 and inverter 704 .
- SR flip-flop 700 detects when the internal clock signal CK I is within a phase detection window.
- SR flip-flop 702 detects when the internal clock signal CK I is in phase with the external clock signal CK E . Once the internal clock signal CK I is in phase with the external clock signal CK E the SW signal is set to logic ‘0’ to disable further changes to the DCDL delay.
- the lock detector output SW is set to logic ‘0’ prior to lock being reached and set to logic ‘1’ after lock is reached.
- the logic ‘0’ on the SW signal couples the fixed bias voltage through multiplexor 314 to provide the VCDL bias voltage 322 .
- the logic ‘1’ on SW couples the variable bias voltage V BPN2 , V BPN2 through multiplexor 314 to provide the VCDL bias voltage 322 , to allow the VCDL 312 to fine tune the overall delay.
- the reset signal coupled to the R-input of the SR flip-flop 700 and the SR flip-flop 702 is set to logic ‘1’. Both flip-flops 700 , 702 are reset with the respective Q outputs (LC 1 , SW) set to logic ‘0’.
- the SR flip-flops 700 , 702 remain in a reset state with logic ‘0’ on the respective Q outputs until the phase detector 320 detects that the phase difference between clock signals CK E , CK I are in the phase detection window.
- the phase difference is within the phase detection window while the rising edge of the internal clock signal CK I is after the falling edge of the external clock signal CK E .
- the output of the phase detector (Ph_det) changes to logic ‘0’.
- Ph_det changes the S-input of SR flip flop 700 to logic ‘1’ through inverter 704 which sets SR flip-flop 700 (i.e. the Q output changes to logic ‘1’).
- the delay provided by the DCDL 306 continues to increase further delaying the rising edge of the internal clock signal until the internal clock signal and the external clock signals are in phase.
- SR flip-flop 702 is set on the next rising edge of Ph-det which occurs when the rising edge of CK E is detected after the rising edge of CK I .
- the Q output of SR flip-flop 702 is set to logic ‘1’.
- the lock detector 310 remains in a locked state with SW set to logic ‘1’ until the system is reset. While in the locked state, the digital domain no longer controls the delay because, while SW is set to logic ‘1’, the code stored in the counter 308 is frozen to freeze the DCDL delay.
- FIGS. 8A-C are timing diagrams illustrating the relationship of the phase detector output (Ph-det) to the phase difference between the clocks.
- the phase detector 320 FIG. 3
- the rising edge of CK I latches a ‘1’ on the Ph_det output of the D-type flip-flop.
- the CK E rising edge continues to increment the code to add additional delay to the DCDL.
- the phase detector detects that the CK I rising edge is now after the falling edge of CK E .
- the rising edge of CK I latches a ‘0’ on the Ph_det output of the D-type flip-flop.
- the CK E rising edge increments the code to add further delay cells to the DCDL.
- the phase detector detects the lock condition when the CK I rising edge moves after the CK E rising edge.
- the rising edge of CK I latches a ‘1’ on the Ph_det output of the D-type flip-flop.
- FIG. 9 is a timing diagram illustrating signals in the schematic shown in FIG. 7 .
- the timing diagram shows the state of signals in the schematic when the system is reset, upon detecting that the phase detection window has been reached and upon detecting lock.
- FIG. 9 is described in conjunction with FIG. 3 and FIG. 7 .
- the system is reset and the reset signal set to logic ‘1’.
- the reset signal is coupled to the R-inputs of flip-flops 700 , 702 to reset the flip-flops.
- the Ph_det signal is reset to logic ‘1’.
- the Q outputs (LC 1 , SW) of both flip-flops are reset to ‘0’.
- the internal clock signal CK I has the same frequency as the external clock signal CK E but there is an initial phase difference due to the delay of CK E through the clock tree buffers 328 .
- the reset signal changes to logic ‘0’.
- Initially delay is added to CK E through the VCDL and no delay is added through the DCDL.
- the rising edge of CK I occurs later than the rising edge of CK E due to the delay through the clock tree buffers 328 ( FIG. 3 ) and the delay through the VCDL.
- the SW signal set to logic ‘0’ allows CK E to increment the code stored in the counter 308 ( FIG. 3 ).
- the delay between CK E and CK I increases until the phase detection window is reached.
- the phase detector 320 detects that the phase detection window has been reached.
- the Ph_det signal output from the phase detector changes state from logic ‘1’ to logic ‘0’ indicating that the phase detector 320 has detected a rising edge of CK I signal after a falling edge of CK E .
- SR flip-flop 600 is set, and LC 1 at the Q output is set to ‘1’. In successive clock periods, the phase difference between Ck E and Ck I decreases as the DCDL delay is increased.
- the phase detector 320 ( FIG. 3 ) detects that the minimum DCDL delay has been added by the DCDL; that is the rising edge of CK I occurred after the rising edge of CK E .
- the Ph-det output of the phase detector 320 changes to logic ‘1’.
- LC 2 at the output of AND gate 706 changes to logic ‘1’, the SR flip-flop 702 is set and the Q output (SW) changes to logic ‘1’. Further changes on the Ph-det signal do not affect the state of LC 1 and SW.
- the SW signal set to ‘1’ disables further incrementing of the counter 308 .
- the delay adjustment of the clock path to compensate for drifts and condition changes covers a narrow range of the wide delay range.
- the DCDL provides the minimum delay.
- the DLL delay is varied by the VCDL inside a smaller delay range. Monitoring the smaller delay range during normal operation provides more stability and reduces the controlling voltage node sensitivity.
- the invention has been described for an embodiment having a single fixed bias voltage level.
- more than one fixed bias voltage level can be used to provide a more compact DLL that is less noise sensitive.
- This allows the wide delay range to be modified in order to reduce the number of DCDL delay elements by selecting a fixed bias voltage level dependent on the frequency of the external clock. Reducing the number of DCDL delay elements, reduces sensitivity to noise. For example, in one embodiment, with a fixed bias voltage of 0.6V DD , fifteen DCDL delay elements are required to provide the DCDL delay. When the fixed bias voltage is 0.7V DD , only eight DCDL delay elements are required to provide the DCDL delay. However, changing the delay range may result in the delay range covering an unstable region, for example, at point C in the graph shown in FIG. 2 .
- the invention can be used in integrated circuits requiring high accuracy of input/output data synchronization, for example, in memory integrated circuits.
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Abstract
Description
- This application is a continuation of U.S. application Ser. No. 13/850,500, filed Mar. 26, 2013, which is a continuation of U.S. application Ser. No. 13/523,406, filed Jun. 14, 2012, now U.S. Pat. No. 8,411,812 issued Apr. 2, 2013, which is a continuation of U.S. application Ser. No. 13/186,104, filed Jul. 19, 2011, now U.S. Pat. No. 8,213,561, issued Jul. 3, 2012, which is a continuation of U.S. application Ser. No. 11/999,162, filed Dec. 4, 2007, now U.S. Pat. No. 8,000,430, issued Aug. 16, 2011, which is a continuation of U.S. application Ser. No. 10/335,535, filed Dec. 31, 2002, now U.S. Pat. No. 7,336,752, issued Feb. 26, 2008.
- The entire teachings of the above application(s) are incorporated herein by reference.
- Many devices such as synchronous dynamic random access memory (SDRAM) and microprocessors receive an external clock signal generated by an external clock source such as a crystal oscillator. The external clock signal received through an input pad on the device is routed to various circuits within the device through a tree of buffer circuits. The buffer tree introduces a common delay between the external clock and each buffered clock.
- Typically, a delay locked loop (DLL) with an adjustable delay line is used to synchronize the buffered clock signal with the external clock signal by delaying the external clock signal applied to the buffer tree. The DLL includes a phase detector, which detects the phase difference between the external clock signal and a buffered clock signal. Based on the detected phase difference, the DLL synchronizes the buffered clock signal to the external clock signal by adding an appropriate delay to the external clock signal until the buffered external clock signal (the internal clock) is in phase with the external clock signal. The DLL can be implemented as an analog delay locked loop or a digital delay locked loop. In an analog delay locked loop, a voltage controlled delay line is used to delay the external clock signal.
-
FIG. 1 is a block diagram of a prior art analog delay locked loop (DLL) 100. Theanalog DLL 100 synchronizes an internal clock signal CKI with an external clock signal CKE. The external clock CKE signal is coupled to a voltage controlleddelay line 102, and the voltage controlleddelay line 102 is coupled toclock tree buffers 108. The delayed external clock signal CKE is fed into theclock tree buffers 108 where it propagates to the outputs of the tree and is applied to the various circuits. The delay through theclock tree buffer 108 results in a phase difference between the external clock signal CKE and the internal clock signal CKI. The voltage controlleddelay line 102 adds further delay to the external clock signal CKE to synchronize the external and internal clock signals. - To determine the appropriate delay in the delay line, one of the outputs of the
clock tree buffers 108 is coupled to a phase detector 104 where it is compared with the external clock signal CKE. The phase detector 104 detects the phase difference between the internal clock CKI and the external clock CKE. The output of the phase detector 104 is integrated by acharge pump 106 and aloop filter capacitor 112 to provide a variablebias voltage V CTRL 110 for the voltage controlled delay line (VCDL) 102. The bias voltage VCTRL selects the delay to be added to the external clock signal by theVCDL 102 to synchronize the internal clock signal CKI with the external clock signal CKE. - The phase detector 104 can be a D-type flip-flop with the D-input coupled to the external clock signal CKE and the clock input coupled to the internal clock signal CKI. On each rising edge of the internal clock signal CKI, the output of the phase detector 104 indicates whether the rising edge of the internal clock signal is before or after the rising edge of the external clock signal.
- The
analog DLL 100 produces a voltage controlled delay with high accuracy. However performance of the analog DLL varies over a frequency range because of a non-linear control voltage characteristic. -
FIG. 2 is a graph illustrating the non-linear control voltage characteristic for the voltage controlled delay line shown inFIG. 1 . In general, devices support a wide range of external clock frequencies within which an operational frequency is selected for a particular device. In the example shown inFIG. 2 , the device can operate at any frequency between point A and point C. The operational frequency selected is at point B. - As shown, the control voltage characteristic is non-linear: sharp at one end of the control voltage range (point C) and almost flat at the opposite end (point A). This control voltage characteristic results in DLL instability at point C and long lock times at point A. The wide range of frequencies (delays) is controlled by the bias voltage VCTRL.
- Referring to
FIG. 1 , the bias voltage VCTRL is the output of thecharge pump 106, which remains in a high-impedance state most of the time. Any noise on the bias voltage signal VCTL disturbs the output of theanalog DLL 100. For example, if the analog DLL is operating at point B, a small voltage change (ΔV) due to noise results in a large change in delay. Thus, the analog DLL is very sensitive to noise when operating at point B, within the wide frequency range shown from point C to point A. Therefore, the analog DLL is not stable within a wide frequency range. - A digital DLL does not have the stability problem of an analog DLL. However, the accuracy of a digital DLL is not the same as the accuracy of an analog DLL, because the delay is provided by combining fixed quantum (steps) of delay. The smaller the step of delay, the higher the accuracy. However, a decrease in step size results in a corresponding increase in silicon area because more delay elements are required to cover the wide frequency range.
- A delay locked loop, which has high accuracy, good stability and a fast lock time over a wide frequency range is presented. The delay locked loop combines shorter lock time, good accuracy and stability with low power consumption and small silicon area for the delay locked loop operating in a wide range of frequencies.
- The delay locked loop includes a digital delay circuit and an analog delay circuit. The digital delay circuit engages delay elements to provide coarse phase adjustment in the delay locked loop. The analog delay circuit provides a fine phase adjustment in the delay locked loop while the digital delay circuit is held at a fixed delay. A lock detector in the digital delay circuit detects completion of the coarse phase adjustment, freezes the fixed delay upon completion and enables fine phase adjustment.
- The digital delay circuit, which includes a plurality of fixed delay elements, operates in a wide delay range. The analog delay circuit operates in a small delay range within the wide delay range and is held at a second fixed delay until the digital delay circuit completes the coarse phase adjustment.
- The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
-
FIG. 1 is a block diagram of a prior art analog delay locked loop (DLL); -
FIG. 2 is a graph illustrating the non-linear controlling voltage characteristic for the voltage controlled delay line shown inFIG. 1 ; -
FIG. 3 is a block diagram of a wide frequency range delay locked loop according to the principles of the present invention; -
FIGS. 4 , 4A and 4B illustrates delay cells in the DCDL and the VCDL; -
FIG. 5 is a schematic of one embodiment of any one of the delay cells shown inFIG. 4 ; -
FIG. 6 is a graph illustrating the non-linear controlling voltage characteristic for the narrow frequency range of the VCDL in the DLL shown inFIG. 3 ; -
FIG. 7 is a schematic of an embodiment of the lock detector and the analog switch shown inFIG. 3 ; -
FIGS. 8A-C are timing diagrams illustrating the relationship of the phase detector output to the phase difference between the clocks; and -
FIG. 9 is a timing diagram illustrating signals in the schematic shown inFIG. 7 . - While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.
- A description of preferred embodiments of the invention follows.
-
FIG. 3 is a block diagram of a wide frequency range delay locked loop (DLL) 300 according to the principles of the present invention. The widefrequency range DLL 300 has two domains of operation: a digital domain which includes adigital delay circuit 302 and an analog domain which includes ananalog delay circuit 304. - In a DLL, high accuracy, small silicon area usage and lower power are typically achieved using an analog technique, while good stability and shorter lock times are typically achieved with a digital technique. The wide
frequency range DLL 300 combines the two techniques to provide high accuracy, good stability and a fast lock time over a wide frequency range. Thedigital delay circuit 302 is responsible for coarse phase adjustment during initialization and theanalog delay circuit 304 is responsible for fine phase adjustment during normal operation, after coarse phase adjustment is completed by thedigital delay circuit 302. Thedigital delay circuit 302 operates within the wide delay range and brings the delay lockedloop 300 to a stable operation point during power-up initialization. In normal operation, theanalog delay circuit 304 operates within a small delay range of the stable operation point within the wide delay range and maintains the delay locked loop at the stable operation point while thedigital delay circuit 302 is held at a fixed delay. - The overall delay provided by the DLL includes a digitally controlled delay line (DCDL) 306 having a set of delay elements, each having a fixed delay and a voltage controlled delay line (VCDL) 312. The combination of the DCDL delay provided by the
DCDL 306 and the VCDL delay provided by theVCDL 312 provides an accurate delay. Only one of the domains can vary the DLL delay at any time. At power-up initialization, thedigital delay circuit 302 varies the DCDL 306 (coarse delay). After coarse phase adjustment is complete (lock is reached), the DCDL delay is held at a fixed number of DCDL delay elements (frozen) and theanalog delay circuit 304 varies the DLL delay to provide fine phase adjustment by varying the VCDL delay. - The
digital delay circuit 302 operates within the wide delay range to bring theDLL 300 to the operation point (lock) quickly to provide a short lock time. Alock detector 310 in thedigital delay circuit 302 detects when thedigital delay circuit 302 has brought the DLL delay to the stable operation point and enables control of the DLL delay to be switched to theanalog delay circuit 304. - A
phase detector 320 detects the phase difference between the external clock signal CKE and the internal clock signal CKI. Thephase detector 320, can be any phase detector well known to those skilled in the art. In the embodiment shown, the phase detector 320 (FIG. 3 ) includes a D-type flip-flop with CKI connected to the clock input and CKE connected to the D-input. The rising edge of CKI latches the state of CKE at the output (Ph_det) of the D-type flip-flop. - The
analog delay circuit 304 includes amultiplexor 314, aVCDL 312 and acharge pump 316. TheVCDL 312 is a chain of differential-input-differential-output stages (delay elements) with voltage control. Themultiplexor 314 selects the source of theVCDL bias voltage 322 to theVCDL 312. TheVCDL bias voltage 322 is a fixed bias voltage VBPI, VBNI provided bybias voltage generator 318 or a variable bias voltage VBP2, VBN2 provided bycharge pump 316. During initialization, before theDCDL 306 achieves lock, differential bias voltage VBPI, VBNI provides theVCDL bias voltage 322 throughmultiplexor 314. Thus, while thedigital delay circuit 302 selects the DCDL delay, theVCDL bias voltage 322 provides a constant VCDL delay. That delay may be in the middle of the full delay range of the VCDL to enable fine tuning in both positive and negative directions as discussed below. - At initialization, the code stored in a
counter 308 is initialized to zero, which corresponds to the minimum delay; that is, the minimum number of delay cells in theDCDL 306 that are engaged. Thelock detector 310 allows theDCDL 306 to increase the DCDL delay by adding delay cells as thecounter 318 is incremented until the nearest rising edge of the internal clock signal CKI is aligned with the external clock signal CKE. Thecounter 308 is incremented by the external clock signal CKE until lock is reached (the clocks are aligned). In one embodiment, thecounter 308 is an up counter which increments on each rising edge of the external clock signal CKE while enabled by the SW signal from thelock detector 310. Delay cells in theDCDL 306 are added to the DCDL delay line based on the n-bit count value output by thecounter 308 to engage the minimum number of DCDL delay cells necessary dependent on the bias voltage VBP1, VBN1. - After the clocks are aligned, the SW signal output by the
lock detector 310 disables any further incrementing of thecounter 308. TheVCDL bias voltage 322 is provided by bias voltage VBP2, VBN2, the output ofcharge pump 316, throughmultiplexor 314. Thecharge pump 316 can be any charge pump well known to those skilled in the art. - By engaging only the minimum number of delay cells in the
DCDL 306, the overall delay line is minimum length to minimize noise. Once lock is reached, thedigital delay circuit 302 is held at a fixed delay by disabling further incrementing of thecounter 308. Only the VCDL portion of the DLL delay line can be varied by theanalog delay circuit 304. Theanalog delay circuit 304 fine tunes the DLL delay to compensate for all drifts and condition changes to keep the external and internal clock signal edges aligned, by varying the VCDL delay, which is added to the fixed delay provided by the DCDL. The analog controlleddelay line 310 varies the VCDL delay up or down by varying the bias voltage to theVCDL delay cells 402 based on detected phase difference between the clocks. -
FIG. 4 illustrates delay cells in the DCDL and the VCDL. The digitally controlled delay line (DCDL) includes a chain ofDCDL delay cells 400 and the voltage controlled delay line (VCDL) includes a chain ofVCDL delay cells 402. The delay of eachDCDL cell 400 is fixed by permanently connecting the bias voltage for eachDCDL cell 400 to a fixed bias voltage VBP1, VBN1. The fixed bias voltage VBP1, VBN1 is provided by a bias voltage generator 318 (FIG. 3 ) which can be any type of voltage stabilizing device, for example, a band-gap reference and need not correspond to theVCDL bias voltage 322 initially applied to the VCDL. - At initialization, none of the
delay elements 400 in theDCDL 306 are engaged. The DLL delay includes only the fixed delay provided bydemultiplexor 404,multiplexor 408 and theVCDL delay elements 402 in the VCDL connected to the fixed bias voltage VBP1, VBN1. The VCDL delay provided by VCDL is dependent on the fixed bias voltage VBP1, VBN1. In the embodiment shown, theDCDL delay cells 400 and theVCDL delay cells 402 are the same delay cell with voltage controlled delay. However, in an alternate embodiment, theDCDL delay cell 400 can differ from theVCDL delay cell 402. - The DCDL is initially variable by increasing the number of
DCDL delay elements 400 with eachDCDL delay element 400 having the same delay fixed by the fixed bias voltage VBP1, VBN1. In the embodiment shown, during initialization the same fixed bias voltage VBP1, VBN1 is coupled to theDCDL delay elements 400 and theVCDL elements 402. However, in alternate embodiments, the fixed bias voltage coupled to theVCDL delay elements 402 and theDCDL delay elements 400 can be different; for example, a first bias voltage may be set to 0.7VDD coupled to the DCDL and a second bias voltage may be set to 0.5VDD coupled to the VCDL. The VCDL delay is initially fixed with each of the threeVCDL delay elements 402 numbered 1-3 coupled to the fixed bias voltage VBP1, VBN1, but the VCDL delay varies with changes in theVCDL bias voltage 322 during normal operation. - The number of engaged elements in the
DCDL 306 is dependent on the n-bit count 406 output by thecounter 308. The n-bit count 406 is coupled to the de-multiplexor 404 to select the output of the de-multiplexor 404 through which the external clock is output to theDCDL 306. The n-bit count 406 is also coupled to multiplexorselect logic 430 which provides an m-bit multiplexor select signal, with one of the m-bits coupled to each multiplexor in theDCDL 306. In one embodiment the multiplexorselect logic 430 is a decoder which decodes the n-bit count to provide the m-bit multiplexor select signal. In the embodiment shown m is 7 and n is 3. There are with sixdelay elements 400 labeled 4-9. The multiplexorselect logic 430 decodes a three bit count 406 to select one of the seven multiplexors through which to forward the external clock as shown in Table 1 below. The Most Significant Bit (MSB) of the seven bit multiplexor select signal corresponds to the select signal formultiplexor 420 and the Least Significant Bit (LSB) of the seven bit multiplexor signal corresponds to the select signal formultiplexor 408. Thus, as the count increases the number of delay elements engaged increases. In an alternate embodiment, the multiplexor select logic can be implemented as a shift register clocked by the external clock and enabled by the SW signal. -
TABLE 1 Count Multiplexor select De-multiplexor select count [2:0] mux_en [6:0] demux_sel[6:0] 000 1111110 1111110 001 1111101 1111101 010 1111011 1111011 011 1110111 1110111 100 1101111 1101111 101 1011111 1011111 110 0111111 0111111 - After lock has been reached, the external clock signal CKE is delayed through DCDL delay elements engaged dependent on the n-bit count output by
counter 308. Control of the DLL delay is switched to theVCDL 312 by switching the bias voltage VBP1, VBN1 to the bias voltage VBP2, VBN2 through the multiplexor 314 (FIG. 3 ). - Thus, the DLL delay includes minimum delay provided by the engaged
DCDL delay elements 400 in theDCDL 306 and additional delay provided by theVCDL 312 to provide an accurate DLL delay. The stability of the DLL is increased by using the digital domain to cover a wide delay range to obtain a minimum delay, then freezing the digital domain to allow the analog domain to operate within a small delay range to control the DLL delay. The bias voltage coupled to theVCDL bias voltage 322 is set so that the VCDL does not control the DLL delay until after lock is detected by the digital domain. Before lock, the VCDL merely provides a constant delay independent of the phase difference between the clocks. - Initially the
counter 308 is reset to 0. The de-multiplexor 404 directs the external clock CLKE to engage delay elements dependent on the n-bit count 406 output by thecounter 308. Withcount 406 set to ‘0’, CLKE is directed throughoutput 422 of de-multiplexor 404 coupled tomultiplexor 408 and nodelay DCDL elements 400 are engaged. - After the
counter 308 is incremented to ‘1’ by CLKE, CLKE is directed throughoutput 424 of the de-multiplexor 404 bycount 406 set to ‘1’ to engage DCDL delay stage labeled 4.Multiplexor 410 is enabled to allow CLKE through toDCDL delay stage 400 labeled 4 and the m-bit multiplexor select signal output by multiplexorselect logic 430 allows delayed CLKE throughmultiplexor 408 to the VCDL. - All six DCDL delay stages are engaged when the
count 406 is six, and CLKE is directed throughde-multiplexor output 426 throughmultiplexors counter 308 is disabled by the SW signal. -
FIG. 5 is a schematic of one embodiment of any one of the delay elements shown inFIG. 4 . Thedelay cell 400 includes a source-coupled pair of NMOS devices T1, T2 withsymmetric loads - The differential input clock signal CLKEI−, CLKEI+, is coupled to the respective gates of NMOS devices T1, T2 with CLKEI+ coupled to the gate of NMOS device T1 and CLKEI− coupled to the gate of NMOS device T2. The differential output clock signal CLKEO−, CLKEO+, is coupled to the respective drains of NMOS devices T1, T2. The sources of NMOS devices T1 and T2 are coupled and are also coupled to the drain of NMOS current source T3. NMOS current source T3 compensates for drain and substrate voltage variations.
-
Symmetric load 500 includes a diode-connected PMOS device T4 connected in parallel with a biased PMOS device T5.Symmetric load 502 includes a diode-connected PMOS device T7 connected in parallel with a biased PMOS device T6. The effective resistance of thesymmetric loads -
FIG. 6 is a graph illustrating the non-linear control voltage characteristic for the narrow delay range of theVCDL 312 in theDLL 300 shown inFIG. 3 . In the embodiment shown, the digital domain provides the minimum delay to bring the operating range of theDLL 300 to point B. After lock, the analog domain operates within anarrow delay range 600 from point B-High to point B-Low. This delay range is much smaller than the wide delay range supported by the DLL, but may be controlled by the same large voltage range as applied in the pure analog case ofFIG. 2 . The small delay range controlled by a large voltage range ensures the stability of the analog domain during normal operation of the DLL. - As shown, the
analog delay circuit 304 operates within the delay range 85 ns to 80 ns over voltage range 200 mV to 800 mV. In contrast to the wide delay range over the same voltage range shown inFIG. 2 , a small variation in control voltage (ΔV) does not substantially affect the delay. -
FIG. 7 is a schematic of an embodiment of thelock detector 310 and themultiplexor 314 shown inFIG. 3 . Thelock detector 310 includes two SR flip-flops gate 706 andinverter 704. SR flip-flop 700 detects when the internal clock signal CKI is within a phase detection window. SR flip-flop 702 detects when the internal clock signal CKI is in phase with the external clock signal CKE. Once the internal clock signal CKI is in phase with the external clock signal CKE the SW signal is set to logic ‘0’ to disable further changes to the DCDL delay. - The lock detector output SW is set to logic ‘0’ prior to lock being reached and set to logic ‘1’ after lock is reached. Prior to lock being reached, the logic ‘0’ on the SW signal couples the fixed bias voltage through
multiplexor 314 to provide theVCDL bias voltage 322. After lock has been reached, the logic ‘1’ on SW couples the variable bias voltage VBPN2, VBPN2 throughmultiplexor 314 to provide theVCDL bias voltage 322, to allow theVCDL 312 to fine tune the overall delay. - On power up, the reset signal coupled to the R-input of the SR flip-
flop 700 and the SR flip-flop 702 is set to logic ‘1’. Both flip-flops flops phase detector 320 detects that the phase difference between clock signals CKE, CKI are in the phase detection window. The phase difference is within the phase detection window while the rising edge of the internal clock signal CKI is after the falling edge of the external clock signal CKE. The output of the phase detector (Ph_det) changes to logic ‘0’. The logic ‘0’ on Ph_det changes the S-input ofSR flip flop 700 to logic ‘1’ throughinverter 704 which sets SR flip-flop 700 (i.e. the Q output changes to logic ‘1’). The delay provided by theDCDL 306 continues to increase further delaying the rising edge of the internal clock signal until the internal clock signal and the external clock signals are in phase. SR flip-flop 702 is set on the next rising edge of Ph-det which occurs when the rising edge of CKE is detected after the rising edge of CKI. The Q output of SR flip-flop 702 is set to logic ‘1’. The logic ‘1’ on the output of SR flip-flop 702, the SW signal, disconnects the VCDL bias signal 322 from bias voltage VBP1, VBN1 throughmultiplexor 314 and connects the bias signal VBP2, VBN2 from charge pump 316 (FIG. 3 ) to theVCDL bias signal 322 to theVCDL 312. - The
lock detector 310 remains in a locked state with SW set to logic ‘1’ until the system is reset. While in the locked state, the digital domain no longer controls the delay because, while SW is set to logic ‘1’, the code stored in thecounter 308 is frozen to freeze the DCDL delay. -
FIGS. 8A-C are timing diagrams illustrating the relationship of the phase detector output (Ph-det) to the phase difference between the clocks. Referring toFIG. 8A , at initialization, the phase detector 320 (FIG. 3 ) detects that the internal clock rising edge is after the external clock rising edge. The rising edge of CKI latches a ‘1’ on the Ph_det output of the D-type flip-flop. The CKE rising edge continues to increment the code to add additional delay to the DCDL. - Referring to
FIG. 8B , the phase detector detects that the CKI rising edge is now after the falling edge of CKE. The rising edge of CKI latches a ‘0’ on the Ph_det output of the D-type flip-flop. The CKE rising edge increments the code to add further delay cells to the DCDL. - Referring to
FIG. 8C , the phase detector detects the lock condition when the CKI rising edge moves after the CKE rising edge. The rising edge of CKI latches a ‘1’ on the Ph_det output of the D-type flip-flop. -
FIG. 9 is a timing diagram illustrating signals in the schematic shown inFIG. 7 . The timing diagram shows the state of signals in the schematic when the system is reset, upon detecting that the phase detection window has been reached and upon detecting lock.FIG. 9 is described in conjunction withFIG. 3 andFIG. 7 . - At time 900, the system is reset and the reset signal set to logic ‘1’. The reset signal is coupled to the R-inputs of flip-
flops - At time 802, after the system is reset, the reset signal changes to logic ‘0’. Initially delay is added to CKE through the VCDL and no delay is added through the DCDL. The rising edge of CKI occurs later than the rising edge of CKE due to the delay through the clock tree buffers 328 (
FIG. 3 ) and the delay through the VCDL. The SW signal set to logic ‘0’ allows CKE to increment the code stored in the counter 308 (FIG. 3 ). As the code stored in the counter 308 (FIG. 3 ) is incremented by CKE (rising edge or falling edge), more delay elements 400 (FIG. 4 ) are added to the DCDL 306 (FIG. 3 ) to further delay CKE. The delay between CKE and CKI increases until the phase detection window is reached. - At
time 904, the phase detector 320 (FIG. 3 ) detects that the phase detection window has been reached. The Ph_det signal output from the phase detector changes state from logic ‘1’ to logic ‘0’ indicating that thephase detector 320 has detected a rising edge of CKI signal after a falling edge of CKE. SR flip-flop 600 is set, and LC1 at the Q output is set to ‘1’. In successive clock periods, the phase difference between CkE and CkI decreases as the DCDL delay is increased. - At
time 906, the phase detector 320 (FIG. 3 ) detects that the minimum DCDL delay has been added by the DCDL; that is the rising edge of CKI occurred after the rising edge of CKE. The Ph-det output of thephase detector 320 changes to logic ‘1’. LC2 at the output of ANDgate 706 changes to logic ‘1’, the SR flip-flop 702 is set and the Q output (SW) changes to logic ‘1’. Further changes on the Ph-det signal do not affect the state of LC1 and SW. The SW signal set to ‘1’ disables further incrementing of thecounter 308. - During normal DLL operation, the delay adjustment of the clock path to compensate for drifts and condition changes covers a narrow range of the wide delay range. Thus, after the lock has been reached, the DCDL provides the minimum delay. The DLL delay is varied by the VCDL inside a smaller delay range. Monitoring the smaller delay range during normal operation provides more stability and reduces the controlling voltage node sensitivity.
- The invention has been described for an embodiment having a single fixed bias voltage level. In an alternate embodiment, more than one fixed bias voltage level can be used to provide a more compact DLL that is less noise sensitive. This allows the wide delay range to be modified in order to reduce the number of DCDL delay elements by selecting a fixed bias voltage level dependent on the frequency of the external clock. Reducing the number of DCDL delay elements, reduces sensitivity to noise. For example, in one embodiment, with a fixed bias voltage of 0.6VDD, fifteen DCDL delay elements are required to provide the DCDL delay. When the fixed bias voltage is 0.7VDD, only eight DCDL delay elements are required to provide the DCDL delay. However, changing the delay range may result in the delay range covering an unstable region, for example, at point C in the graph shown in
FIG. 2 . - The invention can be used in integrated circuits requiring high accuracy of input/output data synchronization, for example, in memory integrated circuits.
- While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims. For example, while the delay of the DCDL remains fixed over short times, it may be allowed to occasionally shift as, for example, the VCDL approaches its delay limits.
Claims (2)
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US14/092,788 US20140084977A1 (en) | 2002-12-31 | 2013-11-27 | Wide Frequency Range Delay Locked Loop |
US15/479,691 US10122369B2 (en) | 2002-12-31 | 2017-04-05 | Wide frequency range delay locked loop |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
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US10/335,535 US7336752B2 (en) | 2002-12-31 | 2002-12-31 | Wide frequency range delay locked loop |
US11/999,162 US8000430B2 (en) | 2002-12-31 | 2007-12-04 | Wide frequency range delay locked loop |
US13/186,104 US8213561B2 (en) | 2002-12-31 | 2011-07-19 | Wide frequency range delay locked loop |
US13/523,406 US8411812B2 (en) | 2002-12-31 | 2012-06-14 | Wide frequency range delay locked loop |
US13/850,500 US8599984B2 (en) | 2002-12-31 | 2013-03-26 | Wide frequency range delay locked loop |
US14/092,788 US20140084977A1 (en) | 2002-12-31 | 2013-11-27 | Wide Frequency Range Delay Locked Loop |
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US13/850,500 Continuation US8599984B2 (en) | 2002-12-31 | 2013-03-26 | Wide frequency range delay locked loop |
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US15/479,691 Continuation US10122369B2 (en) | 2002-12-31 | 2017-04-05 | Wide frequency range delay locked loop |
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2002
- 2002-12-31 US US10/335,535 patent/US7336752B2/en active Active
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2003
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- 2003-12-29 CN CN201210007453.8A patent/CN102522986B/en not_active Expired - Lifetime
- 2003-12-29 EP EP10183259A patent/EP2264902A1/en not_active Withdrawn
- 2003-12-29 ES ES03785447T patent/ES2349123T3/en not_active Expired - Lifetime
- 2003-12-29 KR KR1020057012303A patent/KR101106369B1/en active IP Right Grant
- 2003-12-29 EP EP10171395A patent/EP2251980B1/en not_active Expired - Lifetime
- 2003-12-29 AU AU2003294604A patent/AU2003294604A1/en not_active Abandoned
- 2003-12-29 CN CN2003801078732A patent/CN1732623B/en not_active Expired - Lifetime
- 2003-12-29 DE DE60334032T patent/DE60334032D1/en not_active Expired - Lifetime
- 2003-12-29 KR KR1020107013836A patent/KR101051875B1/en active IP Right Grant
- 2003-12-29 AT AT03785447T patent/ATE480049T1/en not_active IP Right Cessation
- 2003-12-29 EP EP03785447A patent/EP1588489B1/en not_active Expired - Lifetime
- 2003-12-29 WO PCT/CA2003/002040 patent/WO2004059846A1/en not_active Application Discontinuation
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2007
- 2007-12-04 US US11/999,162 patent/US8000430B2/en not_active Expired - Fee Related
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2011
- 2011-07-19 US US13/186,104 patent/US8213561B2/en not_active Expired - Fee Related
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2012
- 2012-06-14 US US13/523,406 patent/US8411812B2/en not_active Expired - Lifetime
- 2012-10-30 HK HK12110872.8A patent/HK1170079A1/en not_active IP Right Cessation
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2013
- 2013-03-26 US US13/850,500 patent/US8599984B2/en not_active Expired - Lifetime
- 2013-11-27 US US14/092,788 patent/US20140084977A1/en not_active Abandoned
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2017
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20150002196A1 (en) * | 2013-06-27 | 2015-01-01 | Micron Technology, Inc. | Semiconductor device having dll circuit |
US9065456B2 (en) * | 2013-06-27 | 2015-06-23 | Micron Technology, Inc. | Semiconductor device having DLL circuit |
US9614533B2 (en) | 2015-06-19 | 2017-04-04 | Intel Corporation | Digital phase control with programmable tracking slope |
US10574241B2 (en) | 2015-06-19 | 2020-02-25 | Intel Corporation | Digital phase control with programmable tracking slope having a programmable linear decoder using a coarse code and a fine code to generate delay adjustments to the phase of an input signal |
CN107809238A (en) * | 2017-09-27 | 2018-03-16 | 珠海格力电器股份有限公司 | Phase-locked loop locking detection method based on MCU and MCU |
Also Published As
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US20130271192A1 (en) | 2013-10-17 |
AU2003294604A1 (en) | 2004-07-22 |
EP2251980B1 (en) | 2012-05-23 |
US10122369B2 (en) | 2018-11-06 |
KR20050091038A (en) | 2005-09-14 |
US20130003483A1 (en) | 2013-01-03 |
ES2349123T3 (en) | 2010-12-28 |
US8599984B2 (en) | 2013-12-03 |
CN1732623A (en) | 2006-02-08 |
CN1732623B (en) | 2012-02-08 |
WO2004059846A1 (en) | 2004-07-15 |
CN102522986A (en) | 2012-06-27 |
US8000430B2 (en) | 2011-08-16 |
US20080089459A1 (en) | 2008-04-17 |
KR101051875B1 (en) | 2011-07-25 |
US20040125905A1 (en) | 2004-07-01 |
US20170272085A1 (en) | 2017-09-21 |
US8213561B2 (en) | 2012-07-03 |
US20110291721A1 (en) | 2011-12-01 |
DE60334032D1 (en) | 2010-10-14 |
EP2264902A1 (en) | 2010-12-22 |
ES2385786T3 (en) | 2012-07-31 |
HK1170079A1 (en) | 2013-02-15 |
ATE480049T1 (en) | 2010-09-15 |
US7336752B2 (en) | 2008-02-26 |
KR20100080864A (en) | 2010-07-12 |
EP1588489B1 (en) | 2010-09-01 |
EP1588489A1 (en) | 2005-10-26 |
US8411812B2 (en) | 2013-04-02 |
EP2251980A1 (en) | 2010-11-17 |
KR101106369B1 (en) | 2012-01-18 |
CN102522986B (en) | 2014-08-13 |
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