US20010015480A1 - Lead frame attachment for optoelectronic device - Google Patents

Lead frame attachment for optoelectronic device Download PDF

Info

Publication number
US20010015480A1
US20010015480A1 US09/733,192 US73319200A US2001015480A1 US 20010015480 A1 US20010015480 A1 US 20010015480A1 US 73319200 A US73319200 A US 73319200A US 2001015480 A1 US2001015480 A1 US 2001015480A1
Authority
US
United States
Prior art keywords
substrate
lead frame
solder bumps
optoelectronic device
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/733,192
Inventor
Brigg Maund
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lumentum Technology UK Ltd
Original Assignee
Bookham Technology PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bookham Technology PLC filed Critical Bookham Technology PLC
Priority to US09/733,192 priority Critical patent/US20010015480A1/en
Publication of US20010015480A1 publication Critical patent/US20010015480A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4256—Details of housings
    • G02B6/4257—Details of housings having a supporting carrier or a mounting substrate or a mounting plate
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236—Fixing or mounting methods of the aligned elements
    • G02B6/4245—Mounting of the opto-electronic elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4246—Bidirectionally operating package structures
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4251—Sealed packages
    • G02B6/4253—Sealed packages by embedding housing components in an adhesive or a polymer material
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4256—Details of housings
    • G02B6/4262—Details of housings characterised by the shape of the housing
    • G02B6/4265—Details of housings characterised by the shape of the housing of the Butterfly or dual inline package [DIP] type
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4266—Thermal aspects, temperature control or temperature monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Optoelectronic devices are known, for example, integrated silicon waveguide devices, which are mounted on a rigid substrate prior to connecting to an electrical lead frame assembly and encapsulation to form a sealed product.
  • integrated silicon waveguide devices having a connection to an optical fibre system, it is important to obtain an maintain correct position and orientation of the waveguide device with the optical fibre. It may also be necessary to form electrical connections to the device from a lead frame assembly and to package the assembly in a sealed manner so as to prevent degradation of operation of the optoelectronic device. For this reason integrated silicon waveguide devices may be mounted on a high mechanical modulus substrate such as a ceramic substrate.
  • the invention provides a method of connecting an optoelectronic device to a lead frame assembly comprising mounting the optoelectronic device on a planar substrate having electrical connecting circuitry for connection to the optoelectronic device, connecting said device to said connecting circuitry, providing a plurality of solder bumps on a major face of the substrate adjacent an edge of the face, the solder bumps being in electrical connection with said connecting circuitry, mounting the substrate on a lead frame support which engages said major face adjacent its periphery, said lead frame support having lead frame conductors exposed on said support so as to contact said solder bumps, and applying heat to melt the solder and thereby form secure electrical connections between the lead frame conductors and the solder bumps.
  • said lead frame support forms part of a casing which is positioned around the substrate and which is sealed to enclose the optoelectronic device.
  • the lead frame support forms part of a mould which surrounds the substrate and the method includes moulding encapsulating material in the mould around the optoelectronic device and substrate to form a sealed product.
  • the lead frame is sealed using an adhesive lid.
  • solder bumps are located on a peripheral region of the substrate between the optoelectronic device and said edge of the face so as to overlie the lead frame conductors when positioned on the lead frame support.
  • solder bumps are provided on the same major face of the substrate as the optoelectronic device and said substrate is inverted to locate the solder bumps under the substrate when the substrate is mounted on the lead frame support.
  • thermal access passages are provided through the thickness of said substrate adjacent said solder bumps and heat is transferred through said passages to melt the solder when connecting the substrate to the lead frame.
  • Thermal access passages may be provided through the lead frame support and heat is transferred through the passages in the lead frame support to melt the solder when connecting the substrate to the lead frame.
  • the substrate may comprise a rigid support providing a connection of fixed relationship of position and direction between an optical fibre and an integrated optical waveguide device which may include an optoelectrical light source or receiver and forming at least part of said optoelectronic device.
  • the optoelectronic device may comprise an integrated silicon chip providing an optical waveguide and may include an optoelectrical light source and/or receiver.
  • the substrate is a ceramic substrate.
  • the invention includes an optoelectronic assembly comprising a planar substrate having electrical connecting circuitry, and an optoelectronic device mounted on said planar substrate and having electrical connection to said electrical connecting circuitry, said substrate being provided with a plurality of solder bumps on a major face of the planar support adjacent an edge of the planar support, said solder bumps being in electrical connection with said electrical connecting circuitry, whereby said assembly may be located on a lead frame support with said solder bumps in engagement with lead frame conductors for securing thereto by application of heat.
  • the invention includes an optoelectronic assembly as aforesaid together with a lead frame assembly comprising a lead frame support with a plurality of lead frame conductors thereon, said support engaging the solder bumps of the planar substrate so that the lead frame conductors are secured to respective solder bumps by heat treatment of the solder bumps.
  • FIG. 1 is a top plan view of an optoelectronic device mounted on a substrate in accordance with the present invention
  • FIG. 2 is a section through the thickness of the assembly shown in FIG. 1,
  • FIG. 3 is an enlarged view of a peripheral region of the substrate used in FIGS. 1 and 2,
  • FIG. 4 is a top plan view of a lead frame and mould assembly for use in accordance with the invention.
  • FIG. 5 is an underplan view of the assembly of FIG. 4,
  • FIG. 6 is a top plan view of the assembly of FIG. 4 when an optoelectronic device has been located in the mould
  • FIG. 7 is a section across the assembly of FIG. 6,
  • FIG. 8 is an underplan view of the assembly of FIG. 6,
  • FIG. 9 is a section across FIG. 8,
  • FIG. 10 shows an alternative structure of lead frame and mould used with an optoelectronic device of the type shown in FIG. 1,
  • FIG. 11 shows the assembly of FIG. 10 when encapsulating material has been used and the mould sealed by lids
  • FIG. 12 shows a variation of FIG. 11 in which different types of encapsulation have been used.
  • FIG. 13 shows a further variation of encapsulation without lids at the mould ends.
  • the optoelectronic device may comprise an integrated silicon waveguide device of the type shown in our UK Patent 2307786. Such a device is shown in FIG. 1 and marked 11 .
  • the device is formed as an integrated silicon chip having thereon one or more waveguides 12 interconnecting optoelectrical devices 13 such as laser diodes or photodiodes.
  • the optical waveguides 12 are connected to an external optical fibre 14 which passes through a feeder channel 15 and is secured on an angled support pad 10 to give the required position and orientation for the connection between the fibre 14 and the waveguides 12 on the chip 11 .
  • a planar substrate 16 which in this example is a high mechanical modulus material formed as a ceramic planar substrate.
  • the substrate is provided with electrical connecting circuitry in the form of a plurality of leads 17 which extend across the substrate to provide an interconnection between the electrical devices on the chip 11 and external contact points 18 on the substrate.
  • the chip 11 is fixed in known manner in a secure position on the substrate 16 and a first wire bonding operation interconnects the devices 13 by wires 19 to the array of leads 17 on the substrate.
  • the substrate itself may have mounted thereon additional electronic devices such as that marked 20 and this is in turn connected to one of the external connections 18 on the substrate.
  • the external electrical connections 18 are formed as solder bumps located on the upper major face of the substrate 16 .
  • the chip 11 is also secured on the same upper major face of the substrate 16 and is positioned away from the edges of the substrate so that the solder bumps 18 lie on the major face adjacent edges of the substrate and are located between the chip 11 and the edges of the substrate.
  • FIG. 3 shows an enlarged view of one solder bump 18 mounted on the substrate 16 and the electrical lead 17 forming a connection with the solder bump 18 is seen extending across the upper surface of the substrate 16 .
  • a thermal passage 22 is provided through the thickness of the substrate 16 adjacent each of the solder bumps 18 so that heat may be transferred through the thermal passage to the solder bump when attaching the assembly to the lead frame.
  • the passageway 22 may be a hollow passage or contain a heat conductor of high thermal conductivity.
  • FIGS. 4 and 5 To mount the device of FIGS. 1 and 2, a lead frame and mould assembly is provided as shown in FIGS. 4 and 5.
  • FIG. 4 shows a rectangular mould wall 25 having on its inner face a lead frame support in the form of a shelf 26 .
  • the shelf 26 surrounds a hollow space and provides a shoulder on which the substrate 16 of FIG. 1 may be supported.
  • An array of lead frame conducting wires 28 extend through the wall 25 on two opposite sides of the rectangular frame and have exposed conductors 30 on the upper surface of the shelf 26 .
  • a projecting channel 31 is provided to hold the optical fibre 14 in position when the assembly of FIG. 1 is located in the frame of FIG. 4.
  • the assembly of FIG. 1 is inverted so that the chip 11 is on the underface of the substrate 16 and the assembly of FIG. 1 then drops into position in the frame of FIG. 4 so that the frame closely surrounds the substrate with the peripheral regions of the major face of the substrate resting on the shoulder 26 .
  • the solder bumps 18 are then resting in face to face engagement with respective wire ends 30 of the lead frame conductors. As shown in FIG.
  • additional bonding strips 36 are provided on the shelf 26 and arranged to engage mating bonding strips 37 on the substrate 16 (shown in FIG. 1). This assists in securing the substrate 16 in the required position with the solder bumps 18 engaging respective lead frame wire ends 30 .
  • the shelf 26 seen from the underside has a plurality of thermal passageways 38 provided through the thickness of the shelf 26 immediately below respective conductor ends 30 .
  • heat and pressure is applied to urge the substrate 16 into contact with the shelf 26 and melt the solder bumps 18 so as to form a secure electrical connection between the solder bumps 18 and respective conductors of the lead frame assembly.
  • solder will solidify leaving permanent electrical connections with the components maintained in their required relative positions.
  • FIG. 6 shows an assembly similar to that of FIG. 1 when it has been inverted and dropped into position in the mould and lead frame assembly of the type shown in FIG. 4.
  • FIG. 6 shows the underface of the substrate 16 and in the particular arrangement shown in FIG. 6 the substrate 16 has thermal passages 22 through the thickness of the substrate to assist in the passage of heat to melt the solder bumps 18 during the bonding operation.
  • the thermal passages 22 provided in the substrate may be in addition to the thermal passages 38 provided through the shelf of the frame 25 .
  • FIG. 7 shows the passages 38 through the shelf 26 lying below the substrate 16 . As illustrated in FIG.
  • FIG. 7 shows the shelf 26 is positioned partway between the opposite ends of the frame so that when the substrate 16 is located in position with the chip 11 on its underface, the contents of the frame are spaced inwardly from the ends so that encapsulating material may be added on both sides of the substrate 16 to encapsulate the assembly and seal the optoelectronic device against the external environment.
  • FIG. 8 shows the underplan view of the assembly in FIG. 6 and is similar to the view of FIG. 5 with the substrate and chip in position.
  • FIG. 9 illustrates the same assembly as FIG. 7 but turned back to the position in which the substrate 16 lies below the chip 11 .
  • solder bump array which overlies the ends of the lead frame conductors 28 in face to face engagement with them, there is no requirement for a second wire bonding operation which would extend the lateral extent of wires from the substrate 16 . Furthermore there is no requirement for the insertion of any wire bonding tool between the edges of the substrate 16 and the surrounding frame 25 . Consequently access is not a problem as the heat and pressure is applied through the top and bottom open ends of the frame 25 through which access is not restricted. It will be understood that the bonds with a plurality, and preferably with all, of the solder bumps 18 are formed simultaneously by a single operation.
  • the package may be sealed in a variety of different ways.
  • the atmosphere within the frame may be purged to provide an inert atmosphere.
  • the starting point for this is illustrated in one example in FIG. 10 when the assembly has been secured in position but no material has been added to either end of the frame 25 to seal the unit.
  • the substrate and chip 11 may be surrounded with a silicone encapsulant material such as is illustrated by 40 and 41 on both sides of the substrate 16 in FIG. 11. Such silicone material may totally encapsulate the substrate 16 and chip 11 although it need not necessarily fill the frame 25 to reach both ends of the frame.
  • the package may be sealed by upper and lower lids 42 and 43 as illustrated in FIG. 11.
  • epoxy resin may be used to fill or partially fill the cavity within the frame 25 .
  • a silicone layer 44 has been used to cover the major face of the substrate on which the chip 11 is mounted. In that way the chip itself is secured within a silicone encapsulant.
  • Epoxy resin is then used as indicated at 45 and 46 to partially fill opposite sides of the frame on both sides of the substrate 16 .
  • Lids 42 and 43 enclose the package as already described with reference to FIG. 11 in the case of an alternative arrangement shown in FIG. 13 the face of the substrate 16 on which the chip 11 is mounted is encased in a silicone layer 44 similar to that shown in FIG. 12. In this case the remainder of the cavity within the mould frame 25 is filled with epoxy material 47 and 48 on opposite sides of the substrate 16 so that the frame is completely filled with epoxy resin flush with opposite ends of the package. In such an arrangement no additional lids 42 and 43 are required.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Led Device Packages (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Light Receiving Elements (AREA)
  • Semiconductor Lasers (AREA)

Abstract

An optoelectronic device is mounted on a planar substrate in electrical connection with solder bumps adjacent an edge of the substrate and connection to a lead frame is made by loading the edge of the substrate on a lead frame support with lead frame conductors in engagement with the solder bumps and applying heat to melt the solder.

Description

    BACKGROUND OF THE INVENTION
  • Optoelectronic devices are known, for example, integrated silicon waveguide devices, which are mounted on a rigid substrate prior to connecting to an electrical lead frame assembly and encapsulation to form a sealed product. In the case of integrated silicon waveguide devices having a connection to an optical fibre system, it is important to obtain an maintain correct position and orientation of the waveguide device with the optical fibre. It may also be necessary to form electrical connections to the device from a lead frame assembly and to package the assembly in a sealed manner so as to prevent degradation of operation of the optoelectronic device. For this reason integrated silicon waveguide devices may be mounted on a high mechanical modulus substrate such as a ceramic substrate. It has been known to locate such substrates within a premoulded encapsulating casing and to form electrical connections between conductors on the substrate and conductors of a lead frame assembly. Known techniques for interconnection of a ceramic substrate have involved wire bonding from the substrate to the lead frame. This may represent a second wire bonding operation in cases where the optoelectronic device has itself required a first wire bonding operation to connect electrical devices to a conducting network on the substrate. In cases where the substrate is located within the walls of a package, restricted access can present problems in making wire bonded connections inside the walls of the package. Furthermore there may be reduced electrical performance due to the length of wire bonds necessary to connect the substrate to the lead frame. [0001]
  • It is an object of the present invention to provide improved method and apparatus for connecting a supporting substrate to a lead frame particularly when forming an enclosed package. [0002]
    • SUMMARY OF THE INVENTION
  • The invention provides a method of connecting an optoelectronic device to a lead frame assembly comprising mounting the optoelectronic device on a planar substrate having electrical connecting circuitry for connection to the optoelectronic device, connecting said device to said connecting circuitry, providing a plurality of solder bumps on a major face of the substrate adjacent an edge of the face, the solder bumps being in electrical connection with said connecting circuitry, mounting the substrate on a lead frame support which engages said major face adjacent its periphery, said lead frame support having lead frame conductors exposed on said support so as to contact said solder bumps, and applying heat to melt the solder and thereby form secure electrical connections between the lead frame conductors and the solder bumps. [0003]
  • Preferably said lead frame support forms part of a casing which is positioned around the substrate and which is sealed to enclose the optoelectronic device. [0004]
  • Preferably the lead frame support forms part of a mould which surrounds the substrate and the method includes moulding encapsulating material in the mould around the optoelectronic device and substrate to form a sealed product. Alternatively the lead frame is sealed using an adhesive lid. [0005]
  • Preferably the solder bumps are located on a peripheral region of the substrate between the optoelectronic device and said edge of the face so as to overlie the lead frame conductors when positioned on the lead frame support. [0006]
  • Preferably the solder bumps are provided on the same major face of the substrate as the optoelectronic device and said substrate is inverted to locate the solder bumps under the substrate when the substrate is mounted on the lead frame support. [0007]
  • Preferably pressure as well as heat is applied to urge the substrate into engagement with the lead frame support to cause the solder bumps to form secure electrical connection with the lead frame conductors. [0008]
  • Preferably thermal access passages are provided through the thickness of said substrate adjacent said solder bumps and heat is transferred through said passages to melt the solder when connecting the substrate to the lead frame. [0009]
  • Thermal access passages may be provided through the lead frame support and heat is transferred through the passages in the lead frame support to melt the solder when connecting the substrate to the lead frame. [0010]
  • The substrate may comprise a rigid support providing a connection of fixed relationship of position and direction between an optical fibre and an integrated optical waveguide device which may include an optoelectrical light source or receiver and forming at least part of said optoelectronic device. [0011]
  • The optoelectronic device may comprise an integrated silicon chip providing an optical waveguide and may include an optoelectrical light source and/or receiver. [0012]
  • Preferably the substrate is a ceramic substrate. [0013]
  • The invention includes an optoelectronic assembly comprising a planar substrate having electrical connecting circuitry, and an optoelectronic device mounted on said planar substrate and having electrical connection to said electrical connecting circuitry, said substrate being provided with a plurality of solder bumps on a major face of the planar support adjacent an edge of the planar support, said solder bumps being in electrical connection with said electrical connecting circuitry, whereby said assembly may be located on a lead frame support with said solder bumps in engagement with lead frame conductors for securing thereto by application of heat. [0014]
  • The invention includes an optoelectronic assembly as aforesaid together with a lead frame assembly comprising a lead frame support with a plurality of lead frame conductors thereon, said support engaging the solder bumps of the planar substrate so that the lead frame conductors are secured to respective solder bumps by heat treatment of the solder bumps. [0015]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a top plan view of an optoelectronic device mounted on a substrate in accordance with the present invention, [0016]
  • FIG. 2 is a section through the thickness of the assembly shown in FIG. 1, [0017]
  • FIG. 3 is an enlarged view of a peripheral region of the substrate used in FIGS. 1 and 2, [0018]
  • FIG. 4 is a top plan view of a lead frame and mould assembly for use in accordance with the invention, [0019]
  • FIG. 5 is an underplan view of the assembly of FIG. 4, [0020]
  • FIG. 6 is a top plan view of the assembly of FIG. 4 when an optoelectronic device has been located in the mould, [0021]
  • FIG. 7 is a section across the assembly of FIG. 6, [0022]
  • FIG. 8 is an underplan view of the assembly of FIG. 6, [0023]
  • FIG. 9 is a section across FIG. 8, [0024]
  • FIG. 10 shows an alternative structure of lead frame and mould used with an optoelectronic device of the type shown in FIG. 1, [0025]
  • FIG. 11 shows the assembly of FIG. 10 when encapsulating material has been used and the mould sealed by lids, [0026]
  • FIG. 12 shows a variation of FIG. 11 in which different types of encapsulation have been used, and [0027]
  • FIG. 13 shows a further variation of encapsulation without lids at the mould ends. [0028]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This example relates to the connection of an optoelectronic device to a lead frame in a sealed enclosure. The optoelectronic device may comprise an integrated silicon waveguide device of the type shown in our UK Patent 2307786. Such a device is shown in FIG. 1 and marked [0029] 11. The device is formed as an integrated silicon chip having thereon one or more waveguides 12 interconnecting optoelectrical devices 13 such as laser diodes or photodiodes. The optical waveguides 12 are connected to an external optical fibre 14 which passes through a feeder channel 15 and is secured on an angled support pad 10 to give the required position and orientation for the connection between the fibre 14 and the waveguides 12 on the chip 11.
  • To maintain the correct positioning of the [0030] optical fibre 14 and silicon chip 11 they are both mounted on a planar substrate 16 which in this example is a high mechanical modulus material formed as a ceramic planar substrate. The substrate is provided with electrical connecting circuitry in the form of a plurality of leads 17 which extend across the substrate to provide an interconnection between the electrical devices on the chip 11 and external contact points 18 on the substrate. Firstly the chip 11 is fixed in known manner in a secure position on the substrate 16 and a first wire bonding operation interconnects the devices 13 by wires 19 to the array of leads 17 on the substrate. The substrate itself may have mounted thereon additional electronic devices such as that marked 20 and this is in turn connected to one of the external connections 18 on the substrate.
  • In this example the external [0031] electrical connections 18 are formed as solder bumps located on the upper major face of the substrate 16. The chip 11 is also secured on the same upper major face of the substrate 16 and is positioned away from the edges of the substrate so that the solder bumps 18 lie on the major face adjacent edges of the substrate and are located between the chip 11 and the edges of the substrate. This is shown more clearly in FIG. 3 which shows an enlarged view of one solder bump 18 mounted on the substrate 16 and the electrical lead 17 forming a connection with the solder bump 18 is seen extending across the upper surface of the substrate 16. A thermal passage 22 is provided through the thickness of the substrate 16 adjacent each of the solder bumps 18 so that heat may be transferred through the thermal passage to the solder bump when attaching the assembly to the lead frame. The passageway 22 may be a hollow passage or contain a heat conductor of high thermal conductivity. To mount the device of FIGS. 1 and 2, a lead frame and mould assembly is provided as shown in FIGS. 4 and 5. FIG. 4 shows a rectangular mould wall 25 having on its inner face a lead frame support in the form of a shelf 26. The shelf 26 surrounds a hollow space and provides a shoulder on which the substrate 16 of FIG. 1 may be supported. An array of lead frame conducting wires 28 extend through the wall 25 on two opposite sides of the rectangular frame and have exposed conductors 30 on the upper surface of the shelf 26. At one end of the frame a projecting channel 31 is provided to hold the optical fibre 14 in position when the assembly of FIG. 1 is located in the frame of FIG. 4. The assembly of FIG. 1 is inverted so that the chip 11 is on the underface of the substrate 16 and the assembly of FIG. 1 then drops into position in the frame of FIG. 4 so that the frame closely surrounds the substrate with the peripheral regions of the major face of the substrate resting on the shoulder 26. The solder bumps 18 are then resting in face to face engagement with respective wire ends 30 of the lead frame conductors. As shown in FIG. 4 additional bonding strips 36 are provided on the shelf 26 and arranged to engage mating bonding strips 37 on the substrate 16 (shown in FIG. 1). This assists in securing the substrate 16 in the required position with the solder bumps 18 engaging respective lead frame wire ends 30.
  • As shown in FIG. 5, the [0032] shelf 26 seen from the underside has a plurality of thermal passageways 38 provided through the thickness of the shelf 26 immediately below respective conductor ends 30. When the substrate 16 is located in position, heat and pressure is applied to urge the substrate 16 into contact with the shelf 26 and melt the solder bumps 18 so as to form a secure electrical connection between the solder bumps 18 and respective conductors of the lead frame assembly. When the heat and pressure is removed the solder will solidify leaving permanent electrical connections with the components maintained in their required relative positions.
  • This operation is illustrated in FIGS. [0033] 6 to 9. FIG. 6 shows an assembly similar to that of FIG. 1 when it has been inverted and dropped into position in the mould and lead frame assembly of the type shown in FIG. 4. As the chip has been inverted FIG. 6 shows the underface of the substrate 16 and in the particular arrangement shown in FIG. 6 the substrate 16 has thermal passages 22 through the thickness of the substrate to assist in the passage of heat to melt the solder bumps 18 during the bonding operation. The thermal passages 22 provided in the substrate may be in addition to the thermal passages 38 provided through the shelf of the frame 25. FIG. 7 shows the passages 38 through the shelf 26 lying below the substrate 16. As illustrated in FIG. 7 the shelf 26 is positioned partway between the opposite ends of the frame so that when the substrate 16 is located in position with the chip 11 on its underface, the contents of the frame are spaced inwardly from the ends so that encapsulating material may be added on both sides of the substrate 16 to encapsulate the assembly and seal the optoelectronic device against the external environment. FIG. 8 shows the underplan view of the assembly in FIG. 6 and is similar to the view of FIG. 5 with the substrate and chip in position. FIG. 9 illustrates the same assembly as FIG. 7 but turned back to the position in which the substrate 16 lies below the chip 11.
  • It will be appreciated that by using the solder bump array which overlies the ends of the [0034] lead frame conductors 28 in face to face engagement with them, there is no requirement for a second wire bonding operation which would extend the lateral extent of wires from the substrate 16. Furthermore there is no requirement for the insertion of any wire bonding tool between the edges of the substrate 16 and the surrounding frame 25. Consequently access is not a problem as the heat and pressure is applied through the top and bottom open ends of the frame 25 through which access is not restricted. It will be understood that the bonds with a plurality, and preferably with all, of the solder bumps 18 are formed simultaneously by a single operation.
  • Once the bonding has taken place, the package may be sealed in a variety of different ways. The atmosphere within the frame may be purged to provide an inert atmosphere. The starting point for this is illustrated in one example in FIG. 10 when the assembly has been secured in position but no material has been added to either end of the [0035] frame 25 to seal the unit. The substrate and chip 11 may be surrounded with a silicone encapsulant material such as is illustrated by 40 and 41 on both sides of the substrate 16 in FIG. 11. Such silicone material may totally encapsulate the substrate 16 and chip 11 although it need not necessarily fill the frame 25 to reach both ends of the frame. The package may be sealed by upper and lower lids 42 and 43 as illustrated in FIG. 11. As an alternative epoxy resin may be used to fill or partially fill the cavity within the frame 25. In FIG. 12 a silicone layer 44 has been used to cover the major face of the substrate on which the chip 11 is mounted. In that way the chip itself is secured within a silicone encapsulant. Epoxy resin is then used as indicated at 45 and 46 to partially fill opposite sides of the frame on both sides of the substrate 16. Lids 42 and 43 enclose the package as already described with reference to FIG. 11 in the case of an alternative arrangement shown in FIG. 13 the face of the substrate 16 on which the chip 11 is mounted is encased in a silicone layer 44 similar to that shown in FIG. 12. In this case the remainder of the cavity within the mould frame 25 is filled with epoxy material 47 and 48 on opposite sides of the substrate 16 so that the frame is completely filled with epoxy resin flush with opposite ends of the package. In such an arrangement no additional lids 42 and 43 are required.
  • The invention is not limited to the details of the foregoing examples. [0036]

Claims (21)

1. A method of connecting an optoelectronic device to a lead frame assembly comprising mounting the optoelectronic device on a planar substrate having electrical connecting circuitry for connection to the optoelectronic device, connecting said device to said connecting circuitry, providing a plurality of solder bumps on a major face of the substrate adjacent an edge of the face, the solder bumps being in electrical connection with said connecting circuitry, mounting the substrate on a lead frame support which engages said major face adjacent its periphery, said lead frame support having lead frame conductors exposed on said support so as to contact said solder bumps, and applying heat to melt the solder and thereby form secure electrical connections between the lead frame conductors and the solder bumps.
2. A method according to
claim 1
 in which heat to melt the solder is applied to a plurality of solder bumps simultaneously to bond the bumps to respective lead frame conductors in a single operation.
3. A method according to
claim 1
 in which said lead frame support forms part of a casing which is positioned around the substrate and which is sealed to enclose the optoelectronic device.
4. A method according to
claim 3
 in which the lead frame support forms part of a mould which surrounds the substrate and the method includes moulding encapsulating material in the mould around the optoelectronic device and substrate to form a sealed product.
5. A method according to
claim 1
 in which the solder bumps are located on a peripheral region of the substrate between the optoelectronic device and said edge of the face so as to overlie the lead frame conductors when positioned on the lead frame support.
6. A method according to
claim 5
 in which the solder bumps are provided on the same major face of the substrate as the optoelectronic device and said substrate is inverted to locate the solder bumps under the substrate when the substrate is mounted on the lead frame support.
7. A method according to
claim 5
 in which pressure as well as heat is applied to urge the substrate into engagement with the lead frame support to cause the solder bumps to form secure electrical connection with the lead frame conductors.
8. A method according to
claim 5
 in which thermal access passages are provided through the thickness of said substrate adjacent said solder bumps and heat is transferred through said passages to melt the solder when connecting the substrate to the lead frame.
9. A method according to
claim 5
 in which thermal access passages are provided through the lead frame support and heat is transferred through the passages in the lead frame support to melt the solder when connecting the substrate to the lead frame.
10. A method according to
claim 1
 in which the substrate comprises a rigid support providing a connection of fixed relationship of position and direction between an optical fibre and an integrated optical waveguide device including at least one optoelectrical light source or receiver and forming at least part of said optoelectronic device.
11. A method according to
claim 10
 in which the optoelectronic device comprises an integrated silicon chip providing an optical waveguide and including an optoelectrical light source and/or receiver.
12. A method according to
claim 10
 in which the substrate is a ceramic substrate.
13. A optoelectronic assembly comprising a planar substrate having electrical connecting circuitry, and an optoelectronic device mounted on said planar substrate and having electrical connection to said electrical connecting circuitry, said substrate being provided with a plurality of solder bumps on a major face of the planar support adjacent an edge of the planar support, said solder bumps being in electrical connection with said electrical connecting circuitry, whereby said assembly may be located on a lead frame support with said solder bumps in engagement with lead frame conductors for securing thereto by application of heat.
14. An optoelectronic assembly according to
claim 13
 in which said solder bumps are provided on a peripheral region of a major face of the substrate and located between the optoelectronic device and said edge of the support.
15. An assembly according to
claim 14
 in which thermal conducting passages are provided through the planar support adjacent said solder bumps.
16. An optoelectronic assembly according to
claim 14
 together with a lead frame assembly comprising a lead frame support with a plurality of lead frame conductors thereon, said support engaging the solder bumps of the planar substrate so that the lead frame conductors are secured to respective solder bumps by heat treatment of the solder bumps.
17. An assembly according to
claim 16
 in which securing means are located between edge regions of the substrate and the lead frame support to secure the substrate in position on the support.
18. An optoelectronic assembly according to
claim 16
 in which the lead frame support forms part of a casing which is positioned around the substrate and which is sealed to enclose the optoelectronic device.
19. An assembly according to
claim 18
 in which the lead frame support forms part of a mould surrounding the substrate, said mould containing encapsulating material around the optoelectronic device and substrate to form a sealed product.
20. An assembly according to
claim 16
 in which the solder bumps are located on the same face of the substrate as the optoelectronic device and said substrate is inverted to locate the solder bumps under the substrate in engagement with the lead frame conductors.
21. An assembly according to
claim 16
 in which thermal access passages are provided through the lead frame support for the transfer of heat to the solder bumps during connection of the bumps to the lead frame conductors.
US09/733,192 1998-07-30 2000-12-08 Lead frame attachment for optoelectronic device Abandoned US20010015480A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/733,192 US20010015480A1 (en) 1998-07-30 2000-12-08 Lead frame attachment for optoelectronic device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB9816692A GB2341482B (en) 1998-07-30 1998-07-30 Lead frame attachment for integrated optoelectronic waveguide device
GB9816692.9 1998-07-30
US09/159,256 US6162653A (en) 1998-07-30 1998-09-23 Lead frame attachment for optoelectronic device
US09/733,192 US20010015480A1 (en) 1998-07-30 2000-12-08 Lead frame attachment for optoelectronic device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/159,256 Division US6162653A (en) 1998-07-30 1998-09-23 Lead frame attachment for optoelectronic device

Publications (1)

Publication Number Publication Date
US20010015480A1 true US20010015480A1 (en) 2001-08-23

Family

ID=10836487

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/159,256 Expired - Lifetime US6162653A (en) 1998-07-30 1998-09-23 Lead frame attachment for optoelectronic device
US09/733,192 Abandoned US20010015480A1 (en) 1998-07-30 2000-12-08 Lead frame attachment for optoelectronic device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/159,256 Expired - Lifetime US6162653A (en) 1998-07-30 1998-09-23 Lead frame attachment for optoelectronic device

Country Status (10)

Country Link
US (2) US6162653A (en)
EP (1) EP1101250A1 (en)
JP (1) JP2002521847A (en)
KR (1) KR20010071062A (en)
CN (1) CN1320278A (en)
AU (1) AU4520499A (en)
CA (1) CA2338993A1 (en)
GB (1) GB2341482B (en)
IL (1) IL141177A0 (en)
WO (1) WO2000007247A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787812B2 (en) * 2001-02-24 2004-09-07 Zarlink Semiconductor Ab Active optical device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE20012450U1 (en) * 2000-07-18 2000-11-23 ROSENBERGER Hochfrequenztechnik GmbH & Co. KG, 84562 Mettenheim Housing for an integrated circuit
KR20040027162A (en) * 2002-09-27 2004-04-01 주식회사일진 optical sub-assembly module for optical communication
JP2005073227A (en) * 2003-08-04 2005-03-17 Sharp Corp Image pickup device
US7683480B2 (en) * 2006-03-29 2010-03-23 Freescale Semiconductor, Inc. Methods and apparatus for a reduced inductance wirebond array
KR20120042425A (en) * 2010-10-25 2012-05-03 삼성전자주식회사 Backlight assembly and display apparatus having the same
US10317620B2 (en) 2015-07-01 2019-06-11 Rockley Photonics Limited Interposer beam expander chip

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3757127A (en) * 1970-08-10 1973-09-04 Cogar Corp Photodetector packing assembly
EP0118554B1 (en) * 1982-09-09 1988-01-13 Plessey Overseas Limited Optical device
JPS5947774A (en) * 1982-09-10 1984-03-17 Fuji Electric Co Ltd Photo semiconductor device
US4843188A (en) * 1986-03-25 1989-06-27 Western Digital Corporation Integrated circuit chip mounting and packaging assembly
JP2744273B2 (en) * 1988-02-09 1998-04-28 キヤノン株式会社 Method for manufacturing photoelectric conversion device
US5120678A (en) * 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
JPH04329659A (en) * 1991-05-01 1992-11-18 Hitachi Ltd Hybrid integrated circuit device and manufacture thereof
JPH05218268A (en) * 1992-02-03 1993-08-27 Toppan Printing Co Ltd Semiconductor device
CA2092165C (en) * 1992-03-23 2001-05-15 Tuyosi Nagano Chip carrier for optical device
US5249733A (en) * 1992-07-16 1993-10-05 At&T Bell Laboratories Solder self-alignment methods
US5340771A (en) * 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
US5719436A (en) * 1995-03-13 1998-02-17 Intel Corporation Package housing multiple semiconductor dies
US5655041A (en) * 1995-10-27 1997-08-05 The Trustees Of Princeton University Method and apparatus for active alignment of semiconductor optical waveguides
JPH09148373A (en) * 1995-11-21 1997-06-06 Murata Mfg Co Ltd Radio communication module
KR100186329B1 (en) * 1996-06-14 1999-03-20 문정환 Semiconductor package for charge coupled device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787812B2 (en) * 2001-02-24 2004-09-07 Zarlink Semiconductor Ab Active optical device

Also Published As

Publication number Publication date
WO2000007247A1 (en) 2000-02-10
CN1320278A (en) 2001-10-31
GB9816692D0 (en) 1998-09-30
AU4520499A (en) 2000-02-21
US6162653A (en) 2000-12-19
CA2338993A1 (en) 2000-02-10
JP2002521847A (en) 2002-07-16
GB2341482B (en) 2003-07-09
GB2341482A (en) 2000-03-15
KR20010071062A (en) 2001-07-28
IL141177A0 (en) 2002-02-10
EP1101250A1 (en) 2001-05-23

Similar Documents

Publication Publication Date Title
US6175159B1 (en) Semiconductor package
KR100638379B1 (en) Process for making contact with and housing integrated circuits
US6170996B1 (en) Optical module encapsulated with resin and manufacturing method therefor
US6545345B1 (en) Mounting for a package containing a chip
US6181854B1 (en) Optical module packaged with molded resin
US20180196196A1 (en) Copackaging of asic and silicon photonics
US6425695B1 (en) Optical module and method of manufacturing the same
US20160291269A1 (en) Photonic integrated circuit chip packaging
US7452140B2 (en) Protective sealing of optoelectronic modules
US5834835A (en) Semiconductor device having an improved structure for storing a semiconductor chip
JP2002033438A (en) Resin-sealed circuit device
US10877217B2 (en) Copackaging of asic and silicon photonics
US20010004128A1 (en) Semiconductor package and manufacturing method thereof
US6967395B1 (en) Mounting for a package containing a chip
US20070045859A1 (en) Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
CA2404032A1 (en) Housing assembly for an electronic device
US6162653A (en) Lead frame attachment for optoelectronic device
GB2126795A (en) Optical device
US7592197B2 (en) Image sensor chip package fabrication method
US20040114884A1 (en) Optoelectronic package structure and process for planar passive optical and optoelectronic devices
GB2396963A (en) Semiconductor packaging structure
JP4166759B2 (en) Method for manufacturing package structure of optical device
JP3065753B2 (en) Resin sealing method for semiconductor integrated circuit bare chip, semiconductor device
US7358598B2 (en) Process for fabricating a semiconductor package and semiconductor package with leadframe
CN105810705A (en) Package structure of high-pixel image sensing chip and fabrication method of package structure

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION